公开(公告)号：US20150058667A1

公开(公告)日：2015-02-26

申请号：US14496345

申请日：2014-09-25

Applicant: Intel Corporation

Inventor： Sanjeev Jahagirdar ,  Varghese George ,  John B. Conrad ,  Robert Milstrey ,  Stephen A. Fischer ,  Alon Naveh ,  Shai Rotem

IPC: G06F1/32 ,  G11C7/10 ,  G06F12/08 ,  G06F11/14

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/3275 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/4418 ,  G06F11/1441 ,  G06F12/084 ,  G06F12/0875 ,  G06F2212/281 ,  G06F2212/305 ,  G06F2212/314 ,  G11C7/1072 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/32 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D50/20 ,  Y02P80/11 ,  Y10T307/305 ,  Y10T307/406 ,  Y10T307/582 ,  Y10T307/826

Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

公开(公告)号：US12210900B2

公开(公告)日：2025-01-28

申请号：US17746201

申请日：2022-05-17

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Balaji Vembu ,  Rajkishore Barik ,  Eriko Nurvitadhi ,  Nicolas Galoppo Von Borries ,  Tsung-Han Lin ,  Sanjeev Jahagirdar ,  Vasanth Ranganathan

IPC: G06F9/48 ,  G06T1/20

Abstract: A mechanism is described for facilitating intelligent thread scheduling at autonomous machines. A method of embodiments, as described herein, includes detecting dependency information relating to a plurality of threads corresponding to a plurality of workloads associated with tasks relating to a processor including a graphics processor. The method may further include generating a tree of thread groups based on the dependency information, where each thread group includes multiple threads, and scheduling one or more of the thread groups associated a similar dependency to avoid dependency conflicts.

公开(公告)号：US12039331B2

公开(公告)日：2024-07-16

申请号：US17967283

申请日：2022-10-17

Applicant: Intel Corporation

Inventor： Himanshu Kaul ,  Mark A. Anders ,  Sanu K. Mathew ,  Anbang Yao ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Tatiana Shpeisman ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Balaji Vembu ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Rajkishore Barik ,  Tsung-Han Lin ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC: G06F9/30 ,  G06F7/483 ,  G06F7/544 ,  G06F9/38 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/08 ,  G09G5/393 ,  G06F1/16 ,  G06N20/00 ,  G06T15/00

CPC classification number: G06F9/3001 ,  G06F7/483 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3851 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/08 ,  G09G5/393 ,  G06F1/16 ,  G06F9/30025 ,  G06F9/3013 ,  G06F2207/3824 ,  G06N20/00 ,  G06T15/005

Abstract: One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute an intermediate product of 16-bit operands and to compute a 32-bit sum based on the intermediate product.

公开(公告)号：US20240078630A1

公开(公告)日：2024-03-07

申请号：US18490593

申请日：2023-10-19

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Durgaprasad Bilagi ,  Joydeep Ray ,  Scott Janus ,  Sanjeev Jahagirdar ,  Brent Insko ,  Lidong Xu ,  Abhishek R. Appu ,  James Holland ,  Vasanth Ranganathan ,  Nikos Kaburlasos ,  Altug Koker ,  Xinmin Tian ,  Guei-Yuan Lueh ,  Changliang Wang

IPC: G06T1/60 ,  G06F12/0802 ,  G06N5/04 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06F12/0802 ,  G06N5/04 ,  G06T1/20 ,  G06F2212/251

Abstract: Embodiments described herein are generally directed to improvements relating to power, latency, bandwidth and/or performance issues relating to GPU processing/caching. According to one embodiment, a system includes a producer intellectual property (IP) (e.g., a media IP), a compute core (e.g., a GPU or an AI-specific core of the GPU), a streaming buffer logically interposed between the producer IP and the compute core. The producer IP is operable to consume data from memory and output results to the streaming buffer. The compute core is operable to perform AI inference processing based on data consumed from the streaming buffer and output AI inference processing results to the memory.

公开(公告)号：US20240013338A1

公开(公告)日：2024-01-11

申请号：US18470652

申请日：2023-09-20

Applicant: Intel Corporation

Inventor： Naveen Matam ,  Lance Cheney ,  Eric Finley ,  Varghese George ,  Sanjeev Jahagirdar ,  Altug Koker ,  Josh Mastronarde ,  Iqbal Rajwani ,  Lakshminarayanan Striramassarma ,  Melaku Teshome ,  Vikranth Vemulapalli ,  Binoj Xavier

IPC: G06T1/20 ,  G06F13/40

CPC classification number: G06T1/20 ,  G06F13/4027

Abstract: Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

公开(公告)号：US11797837B2

公开(公告)日：2023-10-24

申请号：US15494971

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Altug Koker ,  Abhishek R. Appu ,  Kamal Sinha ,  Joydeep Ray ,  Balaji Vembu ,  Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Anbang Yao ,  Kevin Nealis ,  Xiaoming Chen ,  John C. Weast ,  Justin E. Gottschlich ,  Prasoonkumar Surti ,  Chandrasekaran Sakthivel ,  Farshad Akhbari ,  Nadathur Rajagopalan Satish ,  Liwei Ma ,  Jeremy Bottleson ,  Eriko Nurvitadhi ,  Travis T. Schluessler ,  Ankur N. Shah ,  Jonathan Kennedy ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC: G06N3/08 ,  G06N20/00 ,  G06N3/063 ,  G06N3/044 ,  G06N3/045 ,  G06N3/048

CPC classification number: G06N3/08 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N20/00 ,  G06N3/048

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

公开(公告)号：US20230334316A1

公开(公告)日：2023-10-19

申请号：US18314450

申请日：2023-05-09

Applicant: Intel Corporation

Inventor： Altug Koker ,  Abhishek R. Appu ,  Kamal Sinha ,  Joydeep Ray ,  Balaji Vembu ,  Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Anbang Yao ,  Kevin Nealis ,  Xiaoming Chen ,  John C. Weast ,  Justin E. Gottschlich ,  Prasoonkumar Surti ,  Chandrasekaran Sakthivel ,  Farshad Akhbari ,  Nadathur Rajagopalan Satish ,  Liwei Ma ,  Jeremy Bottleson ,  Eriko Nurvitadhi ,  Travis T. Schluessler ,  Ankur N. Shah ,  Jonathan Kennedy ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC: G06N3/08 ,  G06N20/00 ,  G06N3/063 ,  G06N3/044 ,  G06N3/045

CPC classification number: G06N3/08 ,  G06N20/00 ,  G06N3/063 ,  G06N3/044 ,  G06N3/045 ,  G06N3/048

Abstract: Described herein is a graphics processor comprising a memory device and a graphics processing cluster coupled with the memory device. The graphics processing cluster includes a plurality of graphics multiprocessors interconnected via a data interconnect. A graphics multiprocessor includes circuitry configured to load a modular neural network including a plurality of subnetworks, each of the plurality of subnetworks trained to perform a computer vision operation on a separate subject.

公开(公告)号：US11756150B2

公开(公告)日：2023-09-12

申请号：US17674781

申请日：2022-02-17

Applicant: Intel Corporation

Inventor： Naveen Matam ,  Lance Cheney ,  Eric Finley ,  Varghese George ,  Sanjeev Jahagirdar ,  Altug Koker ,  Josh Mastronarde ,  Iqbal Rajwani ,  Lakshminarayanan Striramassarma ,  Melaku Teshome ,  Vikranth Vemulapalli ,  Binoj Xavier

IPC: G06T1/20 ,  G06F13/40

CPC classification number: G06T1/20 ,  G06F13/4027

Abstract: Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

公开(公告)号：US11748106B2

公开(公告)日：2023-09-05

申请号：US17683564

申请日：2022-03-01

Applicant: Intel Corporation

Inventor： Liwei Ma ,  Nadathur Rajagopalan Satish ,  Jeremy Bottleson ,  Farshad Akhbari ,  Eriko Nurvitadhi ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Joydeep Ray ,  Balaji Vembu ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC: G06F9/38

CPC classification number: G06F9/3832

Abstract: A mechanism is described for facilitating fast data operations and for facilitating a finite state machine for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting input data to be used in computational tasks by a computation component of a processor including a graphics processor. The method may further include determining one or more frequently-used data values (FDVs) from the data, and pushing the one or more frequent data values to bypass the computational tasks.

公开(公告)号：US11720355B2

公开(公告)日：2023-08-08

申请号：US17834482

申请日：2022-06-07

Applicant: Intel Corporation

Inventor： Himanshu Kaul ,  Mark A. Anders ,  Sanu K. Mathew ,  Anbang Yao ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Tatiana Shpeisman ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Balaji Vembu ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Rajkishore Barik ,  Tsung-Han Lin ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC: G06F9/30 ,  G09G5/393 ,  G06F9/38 ,  G06F7/483 ,  G06F7/544 ,  G06N3/063 ,  G06N3/08 ,  G06N3/044 ,  G06N3/045 ,  G06T15/00 ,  G06N20/00 ,  G06F17/16

CPC classification number: G06F9/3001 ,  G06F7/483 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3851 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/08 ,  G09G5/393 ,  G06F9/3013 ,  G06F9/30025 ,  G06F17/16 ,  G06F2207/3824 ,  G06N20/00 ,  G06T15/005

Abstract: One embodiment provides a graphics processor comprising a memory controller and a graphics processing resource coupled with the memory controller. The graphics processing resource includes circuitry configured to execute an instruction to perform a matrix operation on first input including weight data and second input including input activation data, generate intermediate data based on a result of the matrix operation, quantize the intermediate data to a floating-point format determined based on a statistical distribution of first output data, and output, as second output data, quantized intermediate data in a determined floating-point format.