公开(公告)号：US07573317B2

公开(公告)日：2009-08-11

申请号：US11535065

申请日：2006-09-26

申请人： David Lewis ,  Vaughn Betz ,  Irfan Rahim ,  Peter McElheny ,  Yow-Juang W. Liu ,  Bruce Pedersen

发明人： David Lewis ,  Vaughn Betz ,  Irfan Rahim ,  Peter McElheny ,  Yow-Juang W. Liu ,  Bruce Pedersen

IPC分类号： H03K3/01

CPC分类号： G06F17/5054 ,  H03K5/133 ,  H03K19/00369 ,  H03K2005/00058 ,  H03K2005/00156 ,  H03K2217/0018

摘要： A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.

摘要翻译： 可编程逻辑器件（PLD）包括延迟电路和体偏置发生器。 延迟电路具有被配置为表示PLD中的用户电路实现的延迟的延迟。 体偏置发生器被配置为调整用户电路内的晶体管的体偏置。 体偏置发生器响应于从延迟电路的信号传播延迟导出的电平来调节晶体管的体偏置。

公开(公告)号：US07465971B2

公开(公告)日：2008-12-16

申请号：US11951122

申请日：2007-12-05

申请人： Lakhbeer S. Sidhu ,  Irfan Rahim ,  Jeffrey Watt ,  John Turner

发明人： Lakhbeer S. Sidhu ,  Irfan Rahim ,  Jeffrey Watt ,  John Turner

IPC分类号： H01L29/94

CPC分类号： G11C11/412 ,  H01L27/0207 ,  H01L27/11807

摘要： A configuration memory cell (“CRAM”) for a field programmable gate array (“FPGA”) integrated circuit (“IC”) device is given increased resistance to single event upset (“SEU”). A portion of the gate structure of the input node of the CRAM is increased in size relative to the nominal size of the remainder of the gate structure. Part of the enlarged gate structure is located capacitively adjacent to an N-well region of the IC, and another part is located capacitively adjacent to a P-well region of the IC. This arrangement gives the input node increased capacitance to resist SEU, regardless of the logical level of the input node. The invention is also applicable to any node of any type of memory cell for which increased resistance to SEU is desired.

公开(公告)号：US07361961B2

公开(公告)日：2008-04-22

申请号：US11114455

申请日：2005-04-25

申请人： Irfan Rahim ,  Yow-Juang Bill Liu ,  Jeffrey Watt

发明人： Irfan Rahim ,  Yow-Juang Bill Liu ,  Jeffrey Watt

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/0203 ,  H01L21/823857 ,  H01L27/0922 ,  H01L27/11807 ,  H01L27/11898 ,  Y10S257/903

摘要： An integrated circuit having an enhanced on-off swing for pass gate transistors is provided. The integrated circuit includes a core region that includes core transistors and pass gate transistors. The core transistors have a gate oxide associated with a first thickness, the pass transistors having a gate oxide associated with a thickness that is less than the first thickness. In one embodiment, the material used for the gate oxide of the pass gate transistors has a dielectric constant that is greater than four, while the material used for the gate oxide of the core transistors has a dielectric constant that is less than or equal to four. A method for manufacturing an integrated circuit is also provided.

摘要翻译： 提供了一种具有用于通过栅极晶体管的增强的通断摆幅的集成电路。 集成电路包括具有核心晶体管和栅极晶体管的核心区域。 核心晶体管具有与第一厚度相关的栅极氧化物，所述通过晶体管具有与小于第一厚度的厚度相关联的栅极氧化物。 在一个实施例中，用于栅极晶体管的栅极氧化物的材料具有大于4的介电常数，而用于核心晶体管的栅极氧化物的材料具有小于或等于4的介电常数 。 还提供了一种用于制造集成电路的方法。

公开(公告)号：US20080074145A1

公开(公告)日：2008-03-27

申请号：US11951122

申请日：2007-12-05

申请人： Lakhbeer Sidhu ,  Irfan Rahim ,  Jeffrey Watt ,  John Turner

发明人： Lakhbeer Sidhu ,  Irfan Rahim ,  Jeffrey Watt ,  John Turner

IPC分类号： H03K19/173

CPC分类号： G11C11/412 ,  H01L27/0207 ,  H01L27/11807

摘要： A configuration memory cell (“CRAM”) for a field programmable gate array (“FPGA”) integrated circuit (“IC”) device is given increased resistance to single event upset (“SEU”). A portion of the gate structure of the input node of the CRAM is increased in size relative to the nominal size of the remainder of the gate structure. Part of the enlarged gate structure is located capacitively adjacent to an N-well region of the IC, and another part is located capacitively adjacent to a P-well region of the IC. This arrangement gives the input node increased capacitance to resist SEU, regardless of the logical level of the input node. The invention is also applicable to any node of any type of memory cell for which increased resistance to SEU is desired.

摘要翻译： 用于现场可编程门阵列（“FPGA”）集成电路（“IC”）器件的配置存储单元（“CRAM”）被赋予增加的对单一事件不正常（“SEU”）的阻力。 CRAM的输入节点的栅极结构的一部分相对于栅极结构的其余部分的标称尺寸增大。 放大栅极结构的一部分位于与IC的N阱区电容性相邻的位置，另一部分位于与IC的P阱区电容相邻的位置。 这种布置使得输入节点增加了抵抗SEU的电容，而与输入节点的逻辑电平无关。 本发明也可应用于任何类型的存储器单元的任何节点，其对期望增加的对SEU的抗性。

公开(公告)号：US07242218B2

公开(公告)日：2007-07-10

申请号：US11003586

申请日：2004-12-02

申请人： Rafael Camarota ,  Irfan Rahim ,  Boon Jin Ang ,  Thow Pang Chong

发明人： Rafael Camarota ,  Irfan Rahim ,  Boon Jin Ang ,  Thow Pang Chong

IPC分类号： H03K19/173 ,  H03K19/177 ,  G06F7/38 ,  H01L25/00

CPC分类号： G06F15/7867 ,  H03K19/17732 ,  H03K19/1776 ,  H03K19/17768 ,  H03K19/17772 ,  H03K19/17776

摘要： Techniques for combining volatile and non-volatile programmable logic into one integrated circuit (IC) are provided. An IC is segregated into two portions. A first block of programmable logic is configured by bits stored in on-chip non-volatile memory. A second block of programmable logic is configured by bits stored in off-chip memory. The function of IO banks on the IC is multiplexed between the two logic blocks of the IC. The programmable logic in the first block can be configured and fully functional in a fraction of the time that the programmable logic in the second block can be configured. The programmable logic in the first block can configure fast enough and have enough independence to assist in the configuration of the second block. The non-volatile memory can also provide security features to a user design, such as encryption.

摘要翻译： 提供了将易失性和非易失性可编程逻辑组合到一个集成电路（IC）中的技术。 IC分为两部分。 可编程逻辑的第一块由存储在片上非易失性存储器中的位来配置。 可编程逻辑的第二块由存储在片外存储器中的位配置。 IC上的IO组的功能在IC的两个逻辑块之间复用。 第一块中的可编程逻辑可以在可配置第二块中的可编程逻辑的几分之一时间内配置和完全运行。 第一块中的可编程逻辑可以配置得足够快，并具有足够的独立性来辅助第二块的配置。 非易失性存储器还可以为诸如加密的用户设计提供安全特征。

公开(公告)号：US20070085558A1

公开(公告)日：2007-04-19

申请号：US11638846

申请日：2006-12-13

申请人： Irfan Rahim ,  Peter McElheny ,  John Costello

发明人： Irfan Rahim ,  Peter McElheny ,  John Costello

IPC分类号： G01R31/26

CPC分类号： G11C5/147 ,  H03K19/177

摘要： The present invention optimizes the performance of integrated circuits by adjusting the circuit operating voltage using feedback on process/product parameters. To determine a desired value for the operating voltage of an integrated circuit, a preferred embodiment provides for on-wafer probing of one or more reference circuit structures to measure at least one electrical or operational parameter of the one or more reference circuit structures; determining an adjusted value for the operating voltage based on the measured parameter; and establishing the adjusted value as the desired value for the operating voltage. The reference circuit structures may comprise process control monitor structures or structures in other integrated circuits fabricated in the same production run. In an alternative embodiment, the one or more parameters are directly measured from the integrated circuit whose operating voltage is being adjusted

摘要翻译： 本发明通过使用对过程/产品参数的反馈来调节电路工作电压来优化集成电路的性能。 为了确定集成电路的工作电压的期望值，优选实施例提供一个或多个参考电路结构的片上探测，以测量一个或多个参考电路结构的至少一个电或操作参数; 基于所测量的参数确定所述工作电压的调整值; 并将调整后的值建立为工作电压的期望值。 参考电路结构可以包括在相同生产运行中制造的其它集成电路中的过程控制监视器结构或结构。 在替代实施例中，一个或多个参数是直接从其工作电压正被调整的集成电路测量的

公开(公告)号：US07142009B1

公开(公告)日：2006-11-28

申请号：US10942692

申请日：2004-09-15

申请人： Jeffrey Watt ,  Irfan Rahim

发明人： Jeffrey Watt ,  Irfan Rahim

IPC分类号： H03K19/173 ,  G06F1/26

CPC分类号： H03K19/0008 ,  H03K19/177

摘要： Adaptive regulated power supply voltages are applied to programmable logic integrated circuits. Control circuitry in a programmable logic IC generates control signals that are transmitted to an external voltage regulator. The voltage regulator generates one or more power supply voltages in response to the control signals. The values of control signals determine the target values of the supply voltages. The control circuitry can adapt the power supply voltages to compensate for temperature and process variations on the IC. The power supply voltages can be programmed by a manufacturer or by a user to achieve desired target values. The control circuitry can also put a programmable logic IC into a sleep mode by dropping the high supply voltage to a low value to reduce power consumption during periods of low usage.

摘要翻译： 自适应稳压电源电压被施加到可编程逻辑集成电路。 可编程逻辑IC中的控制电路产生传输到外部电压调节器的控制信号。 电压调节器响应于控制信号产生一个或多个电源电压。 控制信号的值确定电源电压的目标值。 控制电路可以调节电源电压以补偿IC上的温度和工艺变化。 电源电压可以由制造商或用户编程以实现期望的目标值。 控制电路还可以通过将高电源电压降低到低值来将可编程逻辑IC置于睡眠模式，以在低使用期间降低功耗。

公开(公告)号：US07139997B1

公开(公告)日：2006-11-21

申请号：US10844034

申请日：2004-05-11

申请人： Irfan Rahim ,  Bradley Jensen ,  Girish Venkitachalam ,  Hugh Sung-Ki O ,  Susan Falk ,  Priya Selvaraj

发明人： Irfan Rahim ,  Bradley Jensen ,  Girish Venkitachalam ,  Hugh Sung-Ki O ,  Susan Falk ,  Priya Selvaraj

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： Disclosed is a method for checking the operation of an IC mask generation algorithm in which at least a first identifier of the mask generation algorithm is associated with at least a first symbol that is not associated with generating a functional IC feature. The first symbol has a predetermined size and a predetermined shape. A predetermined location on a mask is also associated with the first symbol. A mask diagram on the mask is generated at least partially at the first predetermined location. The size and shape of the mask diagram is then compared with at least a portion of the first predetermined size and the first predetermined shape of the first symbol.

摘要翻译： 公开了一种用于检查IC掩模生成算法的操作的方法，其中至少掩模生成算法的第一标识符与至少与生成功能IC特征相关联的第一符号相关联。 第一符号具有预定尺寸和预定形状。 掩模上的预定位置也与第一符号相关联。 至少部分地在第一预定位置处产生掩模上的掩模图。 然后将掩模图的尺寸和形状与第一符号的第一预定尺寸和第一预定形状的至少一部分进行比较。

公开(公告)号：US07129745B2

公开(公告)日：2006-10-31

申请号：US10865402

申请日：2004-06-10

申请人： David Lewis ,  Vaughn Betz ,  Irfan Rahim ,  Peter McElheny ,  Yow-Juang W. Liu ,  Bruce Pedersen

发明人： David Lewis ,  Vaughn Betz ,  Irfan Rahim ,  Peter McElheny ,  Yow-Juang W. Liu ,  Bruce Pedersen

IPC分类号： H03K19/173

CPC分类号： G06F17/5054 ,  H03K5/133 ,  H03K19/00369 ,  H03K2005/00058 ,  H03K2005/00156 ,  H03K2217/0018

摘要： A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.

公开(公告)号：US20060237784A1

公开(公告)日：2006-10-26

申请号：US11114455

申请日：2005-04-25

申请人： Irfan Rahim ,  Yow-Juang Liu ,  Jeffrey Watt

发明人： Irfan Rahim ,  Yow-Juang Liu ,  Jeffrey Watt

IPC分类号： H01L29/76

CPC分类号： H01L27/0203 ,  H01L21/823857 ,  H01L27/0922 ,  H01L27/11807 ,  H01L27/11898 ,  Y10S257/903

摘要： An integrated circuit having an enhanced on-off swing for pass gate transistors is provided. The integrated circuit includes a core region that includes core transistors and pass gate transistors. The core transistors have a gate oxide associated with a first thickness, the pass transistors having a gate oxide associated with a thickness that is less than the first thickness. In one embodiment, the material used for the gate oxide of the pass gate transistors has a dielectric constant that is greater than four, while the material used for the gate oxide of the core transistors has a dielectric constant that is less than or equal to four. A method for manufacturing an integrated circuit is also provided.

摘要翻译： 提供了一种具有用于通过栅极晶体管的增强的通断摆幅的集成电路。 集成电路包括具有核心晶体管和栅极晶体管的核心区域。 核心晶体管具有与第一厚度相关的栅极氧化物，所述通过晶体管具有与小于第一厚度的厚度相关联的栅极氧化物。 在一个实施例中，用于栅极晶体管的栅极氧化物的材料具有大于4的介电常数，而用于核心晶体管的栅极氧化物的材料具有小于或等于4的介电常数 。 还提供了一种用于制造集成电路的方法。