公开(公告)号：US06529402B1

公开(公告)日：2003-03-04

申请号：US10094533

申请日：2002-03-08

申请人： John E. Andersen ,  Louis Lu-Chen Hsu ,  Li-Kong Wang

发明人： John E. Andersen ,  Louis Lu-Chen Hsu ,  Li-Kong Wang

IPC分类号： G11C1100

CPC分类号： G11C11/417 ,  G11C5/025 ,  G11C8/08

摘要： A stacked block array architecture.for a SRAM memory for low power applications. The architecture turns on only the required data cells and sensing circuitry to access a particular set of data cells of interest. The wordline delay is reduced by using a shorter and wider wordline wire size. Although less power is consumed, the performance is improved by the reduction in loading of wordlines and bitlines.

摘要翻译： 堆叠块阵列架构，用于低功耗应用的SRAM存储器。 该架构仅打开所需的数据单元和感测电路以访问感兴趣的特定数据单元组。 通过使用更短和更宽的字线大小减小字线延迟。 虽然功耗较低，但通过减少字线和位线的负载来提高性能。

公开(公告)号：US06469949B1

公开(公告)日：2002-10-22

申请号：US09854049

申请日：2001-05-11

申请人： Louis L. Hsu ,  Li-Kong Wang

发明人： Louis L. Hsu ,  Li-Kong Wang

IPC分类号： G11C700

CPC分类号： G11C29/802 ,  G11C29/789

摘要： A fuse latch array system for an embedded DRAM (eDRAM) having a micro-cell architecture, a wide data bandwidth and wide internal bus width is disclosed for locatizing all the fuse information for redundancy replacement purposes. The fuse latch array system includes a fuse latch array having a plurality of memory cells where fuse information is scanned therein sequentially or parallel, or a combination thereof to be compatible with conventional fuse latch scanning protocols, during power-on. When the fuse information is stored in the fuse latch array, it is accessed as a page during a page mode operation. The accessed page contains column redundancy information corresponding to the active bank. The fuse latch array is decoded by row and column, so that the memory cell corresponding to the active bank can be easily located, even if there are thousands of banks within the eDRAM. Once the memory cell corresponding to the active bank is located, the column redundancy information is retrieved for use in identifying the defective column of the active bank using a redundant decoder. If more than one group of datalines are provided for repair, multiple parallel decoding is utilized to locate multiple defective columns simultaneously and replace them simultaneously during a redundancy operation using a conventional multiplexer circuit. The page mode operation of the fuse latch array system ensures the redundancy operation is performed within one clock cycle.

摘要翻译： 公开了一种用于具有微小区架构，宽数据带宽和宽内部总线宽度的嵌入式DRAM（eDRAM）的熔丝锁存阵列系统，用于定位所有熔丝信息用于冗余替换目的。 保险丝锁存阵列系统包括具有多个存储单元的熔丝锁存阵列，其中熔丝信息依次或并行扫描，或其组合，以在通电期间与常规熔丝锁定扫描协议兼容。 当保险丝信息存储在熔丝锁存器阵列中时，在页模式操作期间将其作为页访问。 被访问的页面包含对应于活动库的列冗余信息。 熔丝锁存器阵列由行和列进行解码，使得即使在eDRAM内有数千个存储体，也可以容易地定位对应于活动存储体的存储单元。 一旦与活动组相对应的存储单元被定位，则使用冗余解码器来检索列冗余信息以用于识别活动存储体的缺陷列。 如果提供了多组数据库进行修复，则使用多个并行解码同时定位多个有缺陷的列，并在使用常规多路复用器电路的冗余操作期间同时替换它们。 保险丝闩锁阵列系统的页面模式操作确保在一个时钟周期内执行冗余操作。

公开(公告)号：US06452110B1

公开(公告)日：2002-09-17

申请号：US09897889

申请日：2001-07-05

申请人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Carl J. Radens ,  Li-Kong Wang ,  Keith Kwong Hon Wong

发明人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Carl J. Radens ,  Li-Kong Wang ,  Keith Kwong Hon Wong

IPC分类号： H05K109

CPC分类号： H05K3/02 ,  H01L21/288 ,  H01L21/32134 ,  H01L21/76885 ,  Y10T29/49155 ,  Y10T29/49156

摘要： A method and structure for producing metallic polymer conductor lines comprising of an alternative methodology to a traditional damascene approach, called a cloisonne or inverse damascene approach. The cloisonne approach comprises the steps of coating a photosensitive polymer such as pyrrole or aniline with a silver salt on a semiconductor substrate. Using standard photolithography and resist developing techniques, the conducting polymer is exposed to a wet chemical developer, removing a portion of the exposed conducting polymer region, leaving only conducting polymer lines on top of the substrate. Next, an insulating dielectric layer is deposited over the entire structure and a chemical mechanical polish planarization of the insulator is performed creating the conducting polymer lines. Included in another aspect of the invention is a method and structure for a self-planarizing interconnect material comprising a conductive polymer thereby reducing the number of processing steps relative to the prior art.

摘要翻译： 一种用于生产金属聚合物导体线的方法和结构，其包括传统大马士革方法的替代方法，称为景泰蓝或逆大马士革方法。 景泰蓝方法包括在半导体衬底上用银盐将光敏聚合物如吡咯或苯胺涂覆的步骤。 使用标准光刻和抗蚀显影技术，将导电聚合物暴露于湿化学显影剂，除去暴露的导电聚合物区域的一部分，仅在基底顶部留下导电聚合物线。 接下来，在整个结构上沉积绝缘电介质层，并进行绝缘体的化学机械抛光平面化，产生导电聚合物线。 包括在本发明的另一方面中的是一种用于自平坦化互连材料的方法和结构，其包括导电聚合物，从而减少相对于现有技术的加工步骤的数量。

公开(公告)号：US06214653B1

公开(公告)日：2001-04-10

申请号：US09325732

申请日：1999-06-04

申请人： Howard H. Chen ,  Louis L. Hsu ,  Li-Kong Wang

发明人： Howard H. Chen ,  Louis L. Hsu ,  Li-Kong Wang

IPC分类号： H01L2100

CPC分类号： H01L21/76264 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02675 ,  H01L21/02689 ,  H01L21/2022 ,  H01L21/76283 ,  H01L21/84

摘要： A method of forming a semiconductor substrate (and the resulting structure), includes etching a groove into a bulk silicon substrate, forming a dielectric in the groove and planarizing the silicon substrate to form at least one patterned dielectric island in the silicon substrate, forming an amorphous silicon (or SiGe) layer on exposed portions of the silicon substrate and the at least one dielectric island, crystallizing the amorphous silicon (or SiGe) layer using the exposed silicon substrate as a seed, the silicon substrate having direct contact with the formed silicon layer serving as a crystal growth seeding for the crystallization process, and converting the silicon (or SiGe) layer to crystallized silicon, and performing a shallow trench isolation (STI) process, to form oxide isolations between devices.

摘要翻译： 一种形成半导体衬底的方法（以及所得到的结构）包括将槽蚀刻到体硅衬底中，在沟槽中形成电介质并平坦化硅衬底，以在硅衬底中形成至少一个图案化的电介质岛，形成 在硅衬底和至少一个电介质岛的暴露部分上的非晶硅（或SiGe）层，使用暴露的硅衬底作为晶种使非晶硅（或SiGe）层结晶，硅衬底与所形成的硅直接接触 作为用于晶化过程的晶体生长晶种，并且将硅（或SiGe）层转化为结晶硅，并进行浅沟槽隔离（STI）工艺，以在器件之间形成氧化物隔离。

公开(公告)号：US07778351B2

公开(公告)日：2010-08-17

申请号：US10118750

申请日：2002-04-09

申请人： Louis L. Hsu ,  Li-Kong Wang ,  Philip J. Murfet

发明人： Louis L. Hsu ,  Li-Kong Wang ,  Philip J. Murfet

IPC分类号： H03F3/26 ,  H03F3/68 ,  H03F3/04 ,  H04L25/03

CPC分类号： H03K19/00384

摘要： A CMOS receiver system having a tunable receiver having a tunable gain and a bandwidth system is provided. The tunable receiver includes means for receiving input signals; and a control circuit controlled by a control signal for tuning at least one of the gain and the bandwidth of the tunable receiver, wherein the control signal is indicative of a data rate of the input signals. Furthermore, a method is provided for tuning a CMOS receiver receiving input signals. The method includes the steps of receiving at least one control signal, and controlling one of gain and bandwidth of the CMOS receiver in accordance with the at least one control signal, wherein the at least one control signal is indicative of a data rate of the received input signals.

摘要翻译： 提供具有可调谐增益和带宽系统的可调谐接收机的CMOS接收机系统。 可调谐接收机包括用于接收输入信号的装置; 以及由控制信号控制的控制电路，用于调谐可调接收机的增益和带宽中的至少一个，其中控制信号表示输入信号的数据速率。 此外，提供了一种用于调谐接收输入信号的CMOS接收器的方法。 该方法包括以下步骤：接收至少一个控制信号，并根据至少一个控制信号控制CMOS接收机的增益和带宽中的一个，其中至少一个控制信号指示接收的数据速率 输入信号。

公开(公告)号：US20080171418A1

公开(公告)日：2008-07-17

申请号：US12054545

申请日：2008-03-25

申请人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Cart J. Radens ,  Li-Kong Wang ,  Kwong Hon Wong

发明人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Cart J. Radens ,  Li-Kong Wang ,  Kwong Hon Wong

IPC分类号： H01L21/02

CPC分类号： H01C7/005 ,  H01C7/006 ,  H01C17/075 ,  H01G4/18 ,  H01G4/33 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/5328 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for an integrated circuit chip has a logic core which includes a plurality of insulating and conducting levels, an exterior conductor level and passive devices having a conductive polymer directly connected to the exterior conductor level. The passive devices contain RF devices which also includes resistor, capacitor, and/or inductor. The resistors can be serpentine resistors and the capacitors can be interdigitated capacitors.

摘要翻译： 集成电路芯片的方法和结构具有包括多个绝缘和导电水平的逻辑芯，外部导体水平和具有直接连接到外部导体水平的导电聚合物的无源器件。 无源器件包含还包括电阻器，电容器和/或电感器的RF器件。 电阻器可以是蛇形电阻器，电容器可以是交错电容器。

公开(公告)号：US07216284B2

公开(公告)日：2007-05-08

申请号：US10145018

申请日：2002-05-15

申请人： Louis L. Hsu ,  Brian L. Ji ,  Li-Kong Wang

发明人： Louis L. Hsu ,  Brian L. Ji ,  Li-Kong Wang

IPC分类号： G11C29/00

CPC分类号： G11C15/04 ,  G11C15/043

摘要： A content addressable memory (CAM). A data portion of the CAM array includes word data storage. Each word line includes CAM cells (dynamic or static) in the data portion and a common word match line. An error correction (e.g., parity) portion of the CAM array contains error correction cells for each word line. Error correction cells at each word line are connected to an error correction match line. A match on an error correction match line enables precharging a corresponding data match line. Only data on word lines with a corresponding match on an error correction match line are included in a data compare. Precharge power is required only for a fraction (inversely exponentially proportional to the bit length of error correction employed) of the full array.

摘要翻译： 内容可寻址存储器（CAM）。 CAM阵列的数据部分包括字数据存储。 每个字线包括数据部分中的CAM单元（动态或静态）和公共字匹配线。 CAM阵列的纠错（例如，奇偶校验）部分包含每个字线的纠错单元。 每个字线处的误差校正单元连接到纠错匹配线。 纠错匹配线上的匹配可以对相应的数据匹配线进行预充电。 在数据比较中仅包括在纠错匹配行上具有对应匹配的字线上的数据。 预充电功率只需要一个分数（与所使用的误差校正的位长度成反比成正比）的整数组。

公开(公告)号：US07088074B2

公开(公告)日：2006-08-08

申请号：US10039541

申请日：2002-01-02

申请人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Carl J. Radens ,  Li-Kong Wang ,  Kwong Hon Wong

发明人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Carl J. Radens ,  Li-Kong Wang ,  Kwong Hon Wong

IPC分类号： H02J7/00

CPC分类号： H01M10/425 ,  H01L23/58 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15153 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01M2/1066 ,  H01M2/204 ,  H01L2924/00014 ,  H01L2924/00

摘要： A system level device for battery and integrated circuit chip integration comprises at least one battery; at least one integrated circuit chip powered by the at least one battery; and a package connected to any of the at least one battery and the at least one integrated circuit chip, wherein the at least one battery connects to a pair of opposed upright ends of the package, wherein the at least one integrated circuit chip is disposed between the at least one battery and the package, and wherein the at least one integrated circuit chip lays on top of a portion of the package.

摘要翻译： 用于电池和集成电路芯片集成的系统级装置包括至少一个电池; 由所述至少一个电池供电的至少一个集成电路芯片; 以及连接到所述至少一个电池和所述至少一个集成电路芯片中的任一个的封装，其中所述至少一个电池连接到所述封装的一对相对的直立端，其中所述至少一个集成电路芯片设置在 所述至少一个电池和所述封装，并且其中所述至少一个集成电路芯片放置在所述封装的一部分的顶部上。

公开(公告)号：US20050180521A1

公开(公告)日：2005-08-18

申请号：US10708240

申请日：2004-02-18

申请人： Louis Hsu ,  Carl Radens ,  Li-Kong Wang

发明人： Louis Hsu ,  Carl Radens ,  Li-Kong Wang

IPC分类号： H04L1/22 ,  H04L25/02 ,  H04L25/08 ,  H04L27/04

CPC分类号： H04L1/22 ,  H04L25/029 ,  H04L25/08

摘要： An integrated circuit is provided having a plurality of data transmitters, including a plurality of default data transmitters for transmitting data from a plurality of data sources and at least one redundancy data transmitter. A plurality of connection elements are provided having a first, low impedance connecting state and having a second, high impedance, disconnecting state. The connection elements are operable to disconnect a failing data transmitter from a corresponding output signal line and to connect the redundancy data transmitter to that output signal line in place of the failing data transmitter. In one preferred form, the connection elements include a fuse and an antifuse. In another form, the connection elements include micro-electromechanical (MEM) switches. The connecting elements preferably present the low impedance connecting state at frequencies which include signal switching frequencies above about 500 MHz.

摘要翻译： 提供了具有多个数据发送器的集成电路，包括用于从多个数据源发送数据的多个默认数据发送器和至少一个冗余数据发送器。 提供了具有第一低阻抗连接状态并且具有第二高阻抗断开状态的多个连接元件。 连接元件可操作以将故障数据发射器与相应的输出信号线断开连接，并将冗余数据发射机连接到该输出信号线来代替故障数据发射机。 在一个优选形式中，连接元件包括保险丝和反熔丝。 在另一种形式中，连接元件包括微机电（MEM）开关。 连接元件优选地在包括高于约500MHz的信号切换频率的频率处呈现低阻抗连接状态。

公开(公告)号：US06818487B2

公开(公告)日：2004-11-16

申请号：US10631533

申请日：2003-07-31

申请人： Louis L. Hsu ,  Jack Allan Mandelman ,  William Robert Tonti ,  Li-Kong Wang

发明人： Louis L. Hsu ,  Jack Allan Mandelman ,  William Robert Tonti ,  Li-Kong Wang

IPC分类号： H01L2100

CPC分类号： H01L29/66787 ,  H01L27/11 ,  H01L27/1108 ,  H01L29/42384 ,  H01L29/66765 ,  H01L29/78636

摘要： A semiconductor device is presented which includes a self-aligned, planarized thin-film transistor which can be used in various integrated circuit devices, such as static random access memory (SRAM) cells. The semiconductor device has a first field-effect transistor and a second field-effect transistor. The second field-effect transistor overlies the first field-effect transistor, and the first field-effect transistor and the second field-effect transistor share a common gate. The second field-effect transistor includes a source and a drain which are self-aligned to the shared gate in a layer of planarized semiconductor material above the first field-effect transistor. In one embodiment, the second field-effect transistor is a thin-film transistor, and the shared gate has a U-shape wrap-around configuration at a body of the thin-film transistor.

摘要翻译： 提出了一种半导体器件，其包括可用于诸如静态随机存取存储器（SRAM）单元的各种集成电路器件中的自对准的平坦化薄膜晶体管。 半导体器件具有第一场效应晶体管和第二场效应晶体管。 第二场效应晶体管覆盖第一场效应晶体管，第一场效应晶体管和第二场效应晶体管共用公共栅极。 第二场效应晶体管包括在第一场效应晶体管上方的平坦化半导体材料层中与共享栅极自对准的源极和漏极。 在一个实施例中，第二场效应晶体管是薄膜晶体管，并且共享栅极在薄膜晶体管的主体处具有U形环绕配置。