公开(公告)号：US20090008709A1

公开(公告)日：2009-01-08

申请号：US11963668

申请日：2007-12-21

申请人： Joseph A. Yedinak ,  Nathan L. Kraft

发明人： Joseph A. Yedinak ,  Nathan L. Kraft

IPC分类号： H01L29/78

CPC分类号： H01L29/407 ,  H01L21/26586 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/6835 ,  H01L23/4952 ,  H01L23/49816 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7802 ,  H01L29/7804 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7815 ,  H01L29/7828 ,  H01L29/7831 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2224/16 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H02M3/00 ,  H02M3/33592 ,  H02M7/48 ,  Y02B70/1475 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, active trenches extending through the well region and into the drift region where the active trenches define an active area. Inside each of the active trenches is formed a first conductive gate electrode disposed along and insulated from a first trench sidewall, a second conductive gate electrode disposed along and insulated from a second trench sidewall, and a conductive shield electrode disposed between the first and second conductive gate electrodes, wherein the shield electrode is insulated from and extends deeper inside the trench than the first and second conductive gate electrodes. The device also includes source regions having the first conductivity type formed inside the well region and adjacent the active trenches. Electrical contact to the conductive shield electrode can be made inside the active area. The device can also include a perimeter trench extending at least partially around the active trenches such that at least some of the active trenches are perpendicular to the perimeter trench, gate fingers extending from a perimeter gate poly runner located in said perimeter trench, and shield poly fingers extending from a perimeter shield poly runner located in the perimeter trench. The gate fingers are staggered with respect to the shield poly fingers.

摘要翻译： 半导体功率器件包括第一导电类型的漂移区域，在漂移区域上方延伸并具有与第一导电类型相反的第二导电类型的阱区域，有源沟槽延伸穿过阱区域并进入漂移区域，其中有源沟槽 定义一个活动区域。 在每个有源沟槽内部形成有沿第一沟槽侧壁和绝缘的第一导电栅电极，与第二沟槽侧壁绝缘的第二导电栅电极和与第二沟槽侧壁绝缘的第二导电栅电极，以及设置在第一和第二导电之间的导电屏蔽电极 栅电极，其中所述屏蔽电极与所述第一和第二导电栅电极绝缘并且在所述沟槽内更深地延伸。 该器件还包括形成在阱区内并与有源沟槽相邻的具有第一导电类型的源区。 可以在有源区域内与导电屏蔽电极电接触。 该装置还可以包括至少部分地围绕有源沟槽延伸的周边沟槽，使得至少一些有源沟槽垂直于周边沟槽，从位于所述周边沟槽中的周边门多晶硅浇道延伸的栅极指状物以及屏蔽聚 手指从位于周边沟槽中的周边屏蔽多晶硅转轮延伸。 门指与屏蔽多指交错交错。

公开(公告)号：US20090008706A1

公开(公告)日：2009-01-08

申请号：US11964419

申请日：2007-12-26

申请人： Joseph A. Yedinak ,  Nathan L. Kraft ,  Christopher B. Kocon ,  Richard Stokes

发明人： Joseph A. Yedinak ,  Nathan L. Kraft ,  Christopher B. Kocon ,  Richard Stokes

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/407 ,  H01L21/26586 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/6835 ,  H01L23/4952 ,  H01L23/49816 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7802 ,  H01L29/7804 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7815 ,  H01L29/7828 ,  H01L29/7831 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2224/16 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H02M3/00 ,  H02M3/33592 ,  H02M7/48 ,  Y02B70/1475 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor power device includes active trenches that define an active area and an edge area that is located outside of the active area. The active trenches include a lower shield poly, an upper gate poly, a first oxide layer and a second oxide layer wherein the first oxide layer separates the lower shield poly from the upper gate poly and the second oxide layer covers the upper gate poly. The lower shield poly, upper gate poly, first oxide layer and second oxide layer conform to the shape of the active trench and extend from the active trench to a surface of the edge area. The edge area includes a first opening that extends through the first oxide layer to the lower shield poly and a second opening that extends through the second oxide layer to the upper gate poly. The first opening is filled with a conductive material that makes electrical contact with the lower shield poly and the second opening is filled with conductive material that makes electrical contact with the upper gate poly. The lower shield poly is electrically insulated from the substrate. The second oxide layer can be directly over the upper gate poly, the upper gate poly can be directly over the first oxide layer, the first oxide layer can be directly over the lower shield poly, and the first opening can be lower than the second opening. The device can further include a perimeter trench with extensions in the longitudinal direction that are staggered with respect to the active trenches so that there can be offset between the extensions of the perimeter trench and the active trenches.

摘要翻译： 半导体功率器件包括有源沟槽，其限定有源区域和位于有源区域外部的边缘区域。 有源沟槽包括下屏蔽多晶硅，上栅极多晶硅，第一氧化物层和第二氧化物层，其中第一氧化物层将下屏蔽多晶硅与上栅极多晶硅分开，第二氧化物层覆盖上栅极聚合物。 下屏蔽多晶硅，上栅极多晶硅，第一氧化物层和第二氧化物层符合有源沟槽的形状并从有源沟槽延伸到边缘区域的表面。 边缘区域包括延伸穿过第一氧化物层到下屏蔽多孔体的第一开口和延伸穿过第二氧化物层到第二氧化物层的第二开口到上部栅极聚合物。 第一开口填充有导电材料，其与下屏蔽多孔电接触，并且第二开口填充有与上栅极聚电接触的导电材料。 下屏蔽多晶硅与基板电绝缘。 第二氧化物层可以直接在上栅极多晶硅上方，上栅极多晶硅可以直接在第一氧化物层上方，第一氧化物层可以直接在下屏蔽多晶硅上方，并且第一开口可以低于第二开口 。 该装置还可以包括在纵向方向上延伸的周边沟槽，其相对于有源沟槽交错排列，使得可以在周边沟槽和有源沟槽的延伸部之间偏移。

公开(公告)号：US5323036A

公开(公告)日：1994-06-21

申请号：US822732

申请日：1992-01-21

申请人： John M. S. Neilson ,  Frederick P. Jones ,  Joseph A. Yedinak ,  Christopher L. Rexer

发明人： John M. S. Neilson ,  Frederick P. Jones ,  Joseph A. Yedinak ,  Christopher L. Rexer

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/739 ,  H01L27/10 ,  H01L29/78

CPC分类号： H01L29/0696 ,  H01L29/1095 ,  H01L29/7395 ,  H01L29/4238

摘要： In a power FET composed of a substrate having upper and lower surfaces, the FET providing a current flow path between the upper and lower surfaces, and the FET having a plurality of drain regions extending to the substrate upper surface and an insulated gate electrode disposed on the upper surface, the improvement wherein said drain regions are disposed in a hexagonal lattice pattern, and said gate electrode comprises: a plurality of gate segments each covering a respective drain region; and a plurality of connecting segments each connecting together three of said gate segments.

摘要翻译： 在由具有上表面和下表面的衬底构成的功率FET中，FET在上表面和下表面之间提供电流流动路径，并且具有延伸到衬底上表面的多个漏区的FET和设置在衬底上的绝缘栅电极 上表面，其中所述漏极区域以六边形格子图案设置，并且所述栅极电极包括：多个栅极段，每个栅极段覆盖相应的漏极区域; 以及多个连接段，每个连接段将三个所述栅极段连接在一起。

公开(公告)号：US08193581B2

公开(公告)日：2012-06-05

申请号：US12420711

申请日：2009-04-08

申请人： Joseph A. Yedinak ,  Dean E. Probst ,  Ashok Challa ,  Daniel Calafut

发明人： Joseph A. Yedinak ,  Dean E. Probst ,  Ashok Challa ,  Daniel Calafut

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0611 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7811 ,  H01L29/7827 ,  H01L29/872 ,  H01L29/8725

摘要： Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

公开(公告)号：US08174067B2

公开(公告)日：2012-05-08

申请号：US12417586

申请日：2009-04-02

申请人： Joseph A. Yedinak ,  Daniel Calafut ,  Dean E. Probst

发明人： Joseph A. Yedinak ,  Daniel Calafut ,  Dean E. Probst

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0611 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7811 ,  H01L29/7827 ,  H01L29/872 ,  H01L29/8725

摘要： Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

摘要翻译： 公开了具有提供增加的击穿电压和其他益处的特征的示例性功率半导体器件。

公开(公告)号：US08013387B2

公开(公告)日：2011-09-06

申请号：US11964419

申请日：2007-12-26

申请人： Joseph A. Yedinak ,  Nathan L. Kraft ,  Christopher B. Kocon ,  Richard Stokes

发明人： Joseph A. Yedinak ,  Nathan L. Kraft ,  Christopher B. Kocon ,  Richard Stokes

IPC分类号： H01L29/76

CPC分类号： H01L29/407 ,  H01L21/26586 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/6835 ,  H01L23/4952 ,  H01L23/49816 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7802 ,  H01L29/7804 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7815 ,  H01L29/7828 ,  H01L29/7831 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2224/16 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H02M3/00 ,  H02M3/33592 ,  H02M7/48 ,  Y02B70/1475 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor power device includes active trenches that define an active area and an edge area that is located outside of the active area. The active trenches include a lower shield poly, an upper gate poly, a first oxide layer and a second oxide layer wherein the first oxide layer separates the lower shield poly from the upper gate poly and the second oxide layer covers the upper gate poly. The lower shield poly, upper gate poly, first oxide layer and second oxide layer conform to the shapo of the active trench and extend from the active trench to a surface of the edge area. The edge area includes a first opening that extends through the first oxide layer to the lower shield poly and a second opening that extends through the second oxide layer to the upper gate poly.

摘要翻译： 半导体功率器件包括有源沟槽，其限定有源区域和位于有源区域外部的边缘区域。 有源沟槽包括下屏蔽多晶硅，上栅极多晶硅，第一氧化物层和第二氧化物层，其中第一氧化物层将下屏蔽多晶硅与上栅极多晶硅分开，第二氧化物层覆盖上栅极聚合物。 下屏蔽多晶硅，上栅极多晶硅，第一氧化物层和第二氧化物层符合有源沟槽的形状并从有源沟槽延伸到边缘区域的表面。 边缘区域包括延伸穿过第一氧化物层到下屏蔽多孔体的第一开口和延伸穿过第二氧化物层到第二氧化物层的第二开口到上部栅极聚合物。

公开(公告)号：US5218220A

公开(公告)日：1993-06-08

申请号：US789901

申请日：1991-11-12

申请人： John M. S. Neilson ,  Frederick P. Jones ,  Joseph A. Yedinak

发明人： John M. S. Neilson ,  Frederick P. Jones ,  Joseph A. Yedinak

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/42368

摘要： In a power FET composed of a substrate having upper and lower surfaces and having a semiconductor body of a first conductivity type, the body providing a current flow path between the upper and lower surfaces and having at least one body region which extends to said upper surface; and at least one base region extending into the substrate from the upper surface, the base region being of a second conductivity type opposite to the first conductivity type and having an upper portion located adjacent the upper surface of the substrate and a lower portion separated from the upper surface of the substrate by the upper portion, the upper portion defining a channel which is disposed in the current flow path adjacent the upper surface of the substrate, and the FET further having an insulated gate disposed at the upper surface above the body region, an impurity layer region extends into the channel from the upper surface of the substrate for giving the channel a lower impurity density than the lower portion of the base region.

摘要翻译： 在由具有上表面和下表面并且具有第一导电类型的半导体本体的基板组成的功率FET中，主体在上表面和下表面之间提供电流流动通道，并且具有延伸到所述上表面的至少一个主体区域 ; 以及从上表面延伸到基板中的至少一个基极区域，所述基极区域具有与第一导电类型相反的第二导电类型，并且具有邻近基板上表面的上部分， 所述上部设置在与所述基板的上表面相邻的所述电流流路中的通道，所述FET还具有设置在所述主体区域上方的上表面的绝缘栅， 杂质层区域从衬底的上表面延伸到沟道中，以使沟道的杂质密度低于基区的下部。

公开(公告)号：US5164802A

公开(公告)日：1992-11-17

申请号：US672243

申请日：1991-03-20

申请人： Frederick P. Jones ,  Joseph A. Yedinak ,  John M. S. Neilson ,  Robert S. Wrathall ,  Jeffrey G. Mansmann ,  Claire E. Jackoski

发明人： Frederick P. Jones ,  Joseph A. Yedinak ,  John M. S. Neilson ,  Robert S. Wrathall ,  Jeffrey G. Mansmann ,  Claire E. Jackoski

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L29/7803 ,  H01L29/7806 ,  H01L29/7839

摘要： A monolithic semiconductor device comprises a VDMOS transistor having first and second main electrodes and a control electrode, and a lateral MOSFET having first and second main electrodes and a control electrode, wherein one of the first and second electrodes of the lateral MOSFET has a lower doping concentration than that of the first and second main electrodes of the VDMOS transistor for forming a Schottky barrier diode.

公开(公告)号：US08304829B2

公开(公告)日：2012-11-06

申请号：US12408552

申请日：2009-03-20

申请人： Joseph A. Yedinak ,  Ashok Challa

发明人： Joseph A. Yedinak ,  Ashok Challa

IPC分类号： H01L29/66

CPC分类号： H01L29/0634 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/872 ,  H01L29/8725

摘要： Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

公开(公告)号：US08129245B2

公开(公告)日：2012-03-06

申请号：US13219281

申请日：2011-08-26

申请人： Joseph A. Yedinak ,  Nathan L. Kraft ,  Christopher B. Kocon ,  Richard Stokes

发明人： Joseph A. Yedinak ,  Nathan L. Kraft ,  Christopher B. Kocon ,  Richard Stokes

IPC分类号： H01L21/336

CPC分类号： H01L29/407 ,  H01L21/26586 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/6835 ,  H01L23/4952 ,  H01L23/49816 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7802 ,  H01L29/7804 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7815 ,  H01L29/7828 ,  H01L29/7831 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2224/16 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H02M3/00 ,  H02M3/33592 ,  H02M7/48 ,  Y02B70/1475 ,  H01L2924/00 ,  H01L2924/00014

摘要： Methods of manufacturing power semiconductor devices include forming an epitaxial and dielectric layer, patterning and etching the dielectric layer, forming a first oxide layer, forming a first conductive layer on top of the first oxide layer, etching the first conductive layer away inside an active trench, forming a second oxide layer and second conductive layer. The second conductive layer does not extend completely over the first conductive layer in a first region outside of the active trench. The methods further include forming a third oxide layer over the second conductive layer, etching a first opening through the third oxide layer exposing the second conductive layer outside the active trench, etching a second opening through the second oxide layer outside the active trench in the first region exposing the first conductive layer but not the second conductive layer, and filling the first and second openings with conductive material.

摘要翻译： 制造功率半导体器件的方法包括形成外延和电介质层，图案化和蚀刻介电层，形成第一氧化物层，在第一氧化物层的顶部形成第一导电层，在有源沟槽内部蚀刻第一导电层 ，形成第二氧化物层和第二导电层。 第二导电层在有源沟槽外部的第一区域中不完全延伸到第一导电层上。 所述方法还包括在所述第二导电层上形成第三氧化物层，蚀刻通过所述第三氧化物层的第一开口，将所述第二导电层暴露于所述有源沟槽外部，在所述第一导电层中的所述有源沟槽外蚀刻穿过所述第二氧化物层的第二开口 区域暴露第一导电层而不暴露第二导电层，以及用导电材料填充第一和第二开口。