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    Semiconductor memory medium and memory system
    42.
    发明授权
    Semiconductor memory medium and memory system 有权

    公开(公告)号：US11244728B2

    公开(公告)日：2022-02-08

    申请号：US17018147

    申请日：2020-09-11

    Applicant: Kioxia Corporation

    Inventor： Suguru Nishikawa ,  Takehiko Amaki ,  Yoshihisa Kojima ,  Shunichi Igahara

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  G11C16/08

    Abstract: According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.

    Allocation of memory regions of a nonvolatile semiconductor memory for stream-based data writing
    43.
    发明授权
    Allocation of memory regions of a nonvolatile semiconductor memory for stream-based data writing 有权

    公开(公告)号：US11199974B2

    公开(公告)日：2021-12-14

    申请号：US16927492

    申请日：2020-07-13

    Applicant: KIOXIA CORPORATION

    Inventor： Motohiro Matsuyama ,  Yoshihisa Kojima

    IPC: G06F3/06

    Abstract: A semiconductor storage device comprises a nonvolatile semiconductor memory with memory regions, threads, and a controller. Each thread includes a buffer region in which write data from a host are stored before the write data are written to one of the memory regions, and the buffer region of each thread is different from buffer regions of the other threads. The controller receives stream data from the host, each stream data being associated with one of multiple stream identifications, allocates each stream identification to one of the threads according to priority levels assigned to the stream identifications, such that a stream identification assigned a highest priority level is allocated to a thread to which none of other stream identifications are allocated, and writes each stream data stored in the buffer regions to one of the memory regions according to stream identification of the stream data.

    Memory system
    44.
    发明授权
    Memory system 有权

    公开(公告)号：US11114170B2

    公开(公告)日：2021-09-07

    申请号：US16886546

    申请日：2020-05-28

    Applicant: KIOXIA CORPORATION

    Inventor： Takaya Handa ,  Yoshihisa Kojima ,  Kiyotaka Iwasaki

    IPC: G11C16/26 ,  G11C16/08 ,  G11C16/32 ,  G11C16/24 ,  G11C7/10 ,  G11C7/22

    Abstract: A semiconductor memory device includes a memory cell array, an input/output circuit configured to output read data from the semiconductor memory device, a first data latch configured to latch data read from the memory cell array as the read data, a second data latch to which the read data is transferred from the first data latch and from which the read data is transferred to the input/output circuit, a signaling circuit configured to output a ready signal or a busy signal, and a control circuit configured to control the signaling circuit to output the busy signal while the read data is being latched in the first data latch during a read operation performed on the memory cell array and to output the ready signal while the read data latched in the first data latch is being transferred from the first latch to the second latch.

    Memory system and nonvolatile memory
    45.
    发明授权
    Memory system and nonvolatile memory 有权

    公开(公告)号：US10910068B2

    公开(公告)日：2021-02-02

    申请号：US16727488

    申请日：2019-12-26

    Applicant: KIOXIA Corporation

    Inventor： Kazutaka Takizawa ,  Yoshihisa Kojima ,  Masaaki Niijima

    IPC: G11C16/26 ,  G11C16/04 ,  G11C16/22 ,  H01L27/11582 ,  G11C11/56 ,  H01L27/11556

    Abstract: A memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes memory cells at intersection locations of stacked word lines and a memory pillar passing through the word lines in a stacking direction, the word lines including a first group of word lines stacked above a second group of word lines. The controller reads data of a first memory cell in a first read mode and reads data of a second memory cell in a second read mode. The first memory cell is, and the second memory cell is not, at an intersection location of a word line that is in a boundary area of the first and second groups of word lines and the memory pillar. The boundary area is adjacent to a location of the memory pillar where a width of the memory pillar discontinuously changes along the stacking direction.

    Storage device, storage system, and control method
    46.
    发明授权
    Storage device, storage system, and control method 有权

    公开(公告)号：US12293106B2

    公开(公告)日：2025-05-06

    申请号：US17447088

    申请日：2021-09-08

    Applicant: Kioxia Corporation

    Inventor： Takehiko Amaki ,  Shunichi Igahara ,  Toshikatsu Hida ,  Yoshihisa Kojima

    IPC: G06F3/06

    Abstract: According to one embodiment, a storage device comprises a nonvolatile memory, and a controller configured to perform a first data write operation in a first mode, and to perform a second data write operation in a second mode. Data of a first number of bits is written per memory cell in the first mode. Data of a second number of bits is written per memory cell in the second mode. The second number is larger than the first number. The controller reserves one or more free blocks as write destination block candidates of the first data write operation, perform the first data write operation for one of the write destination block candidates, and perform a garbage collection.

    Memory system
    49.
    发明授权
    Memory system 有权

    公开(公告)号：US11790997B2

    公开(公告)日：2023-10-17

    申请号：US17471569

    申请日：2021-09-10

    Applicant: Kioxia Corporation

    Inventor： Tomoya Kamata ,  Yoshihisa Kojima ,  Suguru Nishikawa

    IPC: G11C16/08 ,  G11C16/32 ,  G11C7/22

    CPC classification number: G11C16/32 ,  G11C7/22

    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller configured to cause the nonvolatile memory to execute a first process of reading data based on a first request from a host device. The memory controller is configured to, when the first request is received from the host device while causing the nonvolatile memory to execute a second process, hold interruption of the second process until a first number becomes a first threshold value or more. The first number is a number of the first requests to be performed in the memory controller. The first threshold value is an integer of 2 or more.

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