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    Method to generate porous organic dielectric
    41.
    发明申请
    Method to generate porous organic dielectric 失效
    生成多孔有机电介质的方法

    公开(公告)号：US20050200024A1

    公开(公告)日：2005-09-15

    申请号：US11125549

    申请日：2005-05-10

    申请人： Lawrence Clevenger ,  Stephen Greco ,  Keith Kwietniak ,  Soon-Cheon Seo ,  Chih-Chao Yang ,  Yun-Yu Wang ,  Kwong Wong

    发明人： Lawrence Clevenger ,  Stephen Greco ,  Keith Kwietniak ,  Soon-Cheon Seo ,  Chih-Chao Yang ,  Yun-Yu Wang ,  Kwong Wong

    IPC分类号： H01L21/312 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522

    CPC分类号： H01L21/76843 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76835 ,  H01L21/76856 ,  H01L2221/1036

    摘要： The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features. The insulator includes pores along surface areas of the insulator that are in contact with the liner and the pores exist only along the surface areas that are in contact with the liner (the liner is not within the pores).

    摘要翻译： 本发明提供一种形成集成电路结构中的布线层的方法，该集成电路结构形成有机绝缘体，图案化绝缘体，将衬垫沉积在绝缘体上，并将该结构暴露于等离子体，以在绝缘体旁边的区域中形成孔 衬垫。 衬垫形成得足够薄以允许等离子体穿过衬垫并在绝缘体中形成孔。 在等离子体处理期间，等离子体通过衬垫而不影响衬垫。 在等离子体处理之后，可以沉积另外的衬里材料。 此后，导体被沉积，导体的多余部分从结构中移除，使得导体仅保留在绝缘体的图案化部分内。 该方法产生集成电路结构，其具有具有图案化特征的有机绝缘体，衬里图案化特征的衬垫和填充图案化特征的导体。 绝缘体包括与绝缘体的表面区域相接触的孔，该孔与衬垫接触，并且孔仅沿着与衬垫接触的表面区域（衬里不在孔内）存在。

    MICRO-CAVITY MEMS DEVICE AND METHOD OF FABRICATING SAME
    43.
    发明申请
    MICRO-CAVITY MEMS DEVICE AND METHOD OF FABRICATING SAME 失效
    微孔MEMS器件及其制造方法

    公开(公告)号：US20080092367A1

    公开(公告)日：2008-04-24

    申请号：US11968896

    申请日：2008-01-03

    申请人： Louis Hsu ,  Lawrence Clevenger ,  Timothy Dalton ,  Carl Radens ,  Keith Wong ,  Chih-Chao Yang

    发明人： Louis Hsu ,  Lawrence Clevenger ,  Timothy Dalton ,  Carl Radens ,  Keith Wong ,  Chih-Chao Yang

    IPC分类号： H01H11/00 ,  H01F41/04

    CPC分类号： H01H50/005 ,  H01H2050/007 ,  Y10T29/4902 ,  Y10T29/49105 ,  Y10T29/49147

    摘要： A method of fabricating a MEMS switch having a free moving inductive element within in micro-cavity guided by at least one inductive coil. The switch consists of an upper inductive coil at one end of a micro-cavity; optionally, a lower inductive coil; and a free-moving inductive element preferably made of magnetic material. The coils are provided with an inner permalloy core. Switching is achieved by passing a current through the upper coil, inducing a magnetic field unto the inductive element. The magnetic field attracts the free-moving inductive element upwards, shorting two open conductive wires, closing the switch. When the current flow stops or is reversed, the free-moving magnetic element drops back by gravity to the bottom of the micro-cavity and the conductive wires open. When the chip is not mounted with the correct orientation, the lower coil pulls the free-moving inductive element back at its original position.

    摘要翻译： 一种制造具有由至少一个感应线圈引导的微腔内的自由运动的感应元件的MEMS开关的方法。 开关由微腔一端的上感应线圈组成; 可选地，下感应线圈; 以及优选由磁性材料制成的自由移动的电感元件。 线圈设有内坡道合金芯。 通过使电流通过上部线圈，从而产生电感元件的磁场来实现切换。 磁场向上吸引自由移动的感应元件，短路两根开放的导线，闭合开关。 当电流停止或反转时，自由移动的磁性元件通过重力返回到微腔的底部并且导线打开。 当芯片没有以正确的方向安装时，下线圈将自由移动的感应元件拉回其原始位置。

    ELECTRICAL PROGRAMMABLE METAL RESISTOR
    46.
    发明申请
    ELECTRICAL PROGRAMMABLE METAL RESISTOR 有权
    电可编程金属电阻器

    公开(公告)号：US20060249846A1

    公开(公告)日：2006-11-09

    申请号：US10908360

    申请日：2005-05-09

    申请人： Chih-Chao Yang ,  Lawrence Clevenger ,  James Demarest ,  Louis Hsu ,  Carl Radens

    发明人： Chih-Chao Yang ,  Lawrence Clevenger ,  James Demarest ,  Louis Hsu ,  Carl Radens

    IPC分类号： H01L23/52

    CPC分类号： H01L23/5228 ,  H01L23/5256 ,  H01L23/5329 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides an electrical programmable metal resistor and a method of fabricating the same in which electromigration stress is used to create voids in the structure that increase the electrical resistance of the resistor. Specifically, a semiconductor structure is provided that includes an interconnect structure comprising at least one dielectric layer, wherein said at least one dielectric layer comprises at least two conductive regions and an overlying interconnect region embedded therein, said at least two conductive regions are in contact with said overlying interconnect region by at least two contacts and at least said interconnect region is separated from said at least one dielectric layer by a diffusion barrier, wherein voids are present in at least the interconnect region which increase the electrical resistance of the interconnect region.

    摘要翻译： 本发明提供一种电可编程金属电阻器及其制造方法，其中电迁移应力用于在结构中产生增加电阻器的电阻的空隙。 具体而言，提供一种半导体结构，其包括包括至少一个电介质层的互连结构，其中所述至少一个电介质层包括至少两个导电区域和嵌入其中的覆盖互连区域，所述至少两个导电区域与 所述覆盖互连区域由至少两个触点和至少所述互连区域通过扩散阻挡层与所述至少一个介电层分离，其中空隙存在于至少互连区域中，这增加了互连区域的电阻。

    HEAT DISSIPATION FOR HEAT GENERATING ELEMENT OF SEMICONDUCTOR DEVICE AND RELATED METHOD
    47.
    发明申请
    HEAT DISSIPATION FOR HEAT GENERATING ELEMENT OF SEMICONDUCTOR DEVICE AND RELATED METHOD 有权
    用于半导体器件的发热元件的散热及相关方法

    公开(公告)号：US20060231945A1

    公开(公告)日：2006-10-19

    申请号：US10907873

    申请日：2005-04-19

    申请人： Anil Chinthakindi ,  Lawrence Clevenger ,  Tom Lee ,  Gerald Matusiewicz ,  Conal Murray ,  Chih-Chao Yang

    发明人： Anil Chinthakindi ,  Lawrence Clevenger ,  Tom Lee ,  Gerald Matusiewicz ,  Conal Murray ,  Chih-Chao Yang

    IPC分类号： H01L23/34

    CPC分类号： H01L23/5228 ,  H01L23/3677 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A structure and method are disclosed for heat dissipation relative to a heat generating element in a semiconductor device. The structure includes a plurality of heat transmitting lines partially vertically coincidental with the heat generating element, and at least one interconnecting path from each heat transmitting line to a substrate of the semiconductor device. In one embodiment, the heat generating element includes a resistor in a non-first metal level. The invention is compatible with conventional BEOL interconnect schemes, minimizes the amount of heat transfer from the resistor to the surrounding interconnect wiring, thus eliminating the loss of current carrying capability in the wiring.

    摘要翻译： 公开了相对于半导体器件中的发热元件的散热的结构和方法。 该结构包括多个与发热元件垂直一致的传热线，以及从每个传热线到半导体器件的基板的至少一个互连路径。 在一个实施例中，发热元件包括非第一金属水平的电阻器。 本发明与传统的BEOL互连方案兼容，使得从电阻器到周围互连布线的传热量最小化，从而消除了布线中的载流能力的损失。