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    Semiconductor memory device
    43.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US06940739B2

    公开(公告)日：2005-09-06

    申请号：US10307954

    申请日：2002-12-03

    申请人： Hiroyuki Mizuno ,  Suguru Tachibana ,  Koichiro Ishibashi ,  Kenichi Osada

    发明人： Hiroyuki Mizuno ,  Suguru Tachibana ,  Koichiro Ishibashi ,  Kenichi Osada

    IPC分类号： G11C11/41 ,  G06F12/08 ,  G11C5/06 ,  G11C7/06 ,  G11C7/18 ,  G11C7/22 ,  G11C11/401 ,  G11C11/409

    CPC分类号： G11C7/18 ,  G06F12/0893 ,  G11C5/063 ,  G11C7/06 ,  G11C7/22 ,  G11C2207/108 ,  Y02D10/13

    摘要： A memory structure/circuit has at least two memory cell arrays connected to each other in a hierarchy. The bit lines of the two or more memory cell arrays are connected by hierarchy switches. The memory cells of one of the arrays can be read out faster than the others by using the hierarchy switches to select one array without selecting the other arrays. So the data that is read with higher frequency can be selectively read out faster if it is stored in the faster access memory array. If the data in the faster access memory cell array includes a copy of the data in the other array, it can be used as a cache memory. A tag array and data array in combination that are connected to another tag array and data array in combination through hierarchy switch connections can provide a cache memory that is direct mapped or set associative, and also full associative. The memory device can be used in a semiconductor data processor having a CPU in which the memory device is connected to the CPU through a bus, wherein both the CPU and the memory device are formed on a single semiconductor substrate. The memory device can also be an off-chip device.

    摘要翻译： 存储器结构/电路具有至少两个相互连接的存储单元阵列。 两个或多个存储单元阵列的位线通过分层开关连接。 通过使用层次结构开关选择一个阵列而不选择其他阵列，其中一个阵列的存储单元可以比其他阵列更快地读出。 因此，如果存储在更快的访问存储器阵列中，则可以更快地选择性地读出更高频率读取的数据。 如果快速访问存储单元阵列中的数据包含另一阵列中的数据副本，则可以将其用作高速缓冲存储器。 组合的标签阵列和数据阵列通过分层交换机连接组合连接到另一标签阵列和数据阵列，可以提供直接映射或设置关联的高速缓存存储器，也可以是完全关联的。 存储器件可用于具有CPU的半导体数据处理器，其中存储器件通过总线连接到CPU，其中CPU和存储器件均形成在单个半导体衬底上。 存储器件也可以是片外器件。

    Semiconductor memory device with memory cells operated by boosted voltage
    44.
    发明申请
    Semiconductor memory device with memory cells operated by boosted voltage 有权
    具有由升压电压工作的存储单元的半导体存储器件

    公开(公告)号：US20050024917A1

    公开(公告)日：2005-02-03

    申请号：US10926032

    申请日：2004-08-26

    申请人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

    发明人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

    IPC分类号： G11C11/413 ,  G11C11/41 ,  G11C11/412 ,  G11C11/417 ,  H01L21/8244 ,  H01L27/10 ,  H01L27/11 ,  G11C11/22

    CPC分类号： G11C11/417 ,  G11C11/412 ,  Y10S257/903

    摘要： A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd′ higher than a power supply voltage Vdd of a power supply line for peripheral circuits is supplied from a power supply line for memory cells as a power supply voltage for memory cells. Since the conductance of driver MOS transistors is increased, the threshold voltage of the MOS transistors within the memory cells can be reduced without reducing the static noise margin. Further the ratio of width between the driver MOS transistor and a transfer MOS transistor can be set to 1, thereby allowing a reduction in the memory cell area.

    摘要翻译： 使用用于低电压操作的SRAM存储单元的存储器被设计为降低构成存储器单元的MOS晶体管的阈值，而不会显着降低静态噪声容限，这是存储单元的操作余量。 为此，作为存储单元的电源电压，从用于存储单元的电源线提供高于外围电路用电源线的电源电压Vdd的电压Vdd'。 由于驱动器MOS晶体管的电导增加，所以可以在不降低静态噪声容限的情况下减小存储单元内的MOS晶体管的阈值电压。 此外，可以将驱动器MOS晶体管和转移MOS晶体管之间的宽度比设置为1，从而允许存储单元区域的减小。

    Semiconductor device
    46.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US6058038A

    公开(公告)日：2000-05-02

    申请号：US219429

    申请日：1998-12-23

    申请人： Kenichi Osada ,  Koichiro Ishibashi

    发明人： Kenichi Osada ,  Koichiro Ishibashi

    IPC分类号： G06F12/08 ,  G06F12/10 ,  G11C11/34 ,  G11C15/00 ,  G11C15/04

    CPC分类号： G06F12/1027 ,  G06F12/0864 ,  G11C15/00 ,  G11C15/04

    摘要： A memory device having a plurality of blocks, each of a plurality of blocks comprising a memory array having a plurality of word lines and a plurality of memory cells connected to the word lines, an associative cell array for outputting a hit signal by comparing a first address inputted thereto with internal data and a decoder circuit for selecting one line by decoding a second address and wherein one of the word lines is selected based on the line selected by the decoder circuit and the hit signal.

    摘要翻译： 一种存储器件，具有多个块，多个块中的每一个包括具有多个字线的存储器阵列和连接到所述字线的多个存储器单元;相关单元阵列，用于通过比较第一 用内部数据输入的地址，以及通过解码第二地址来选择一行的解码器电路，并且其中基于由解码器电路选择的行和命中信号来选择一个字线。

    Semiconductor apparatus
    47.
    发明授权
    Semiconductor apparatus 有权
    半导体装置

    公开(公告)号：US08508968B2

    公开(公告)日：2013-08-13

    申请号：US13461848

    申请日：2012-05-02

    申请人： Makoto Saen ,  Kenichi Osada ,  Masanao Yamaoka ,  Tomonori Sekiguchi

    发明人： Makoto Saen ,  Kenichi Osada ,  Masanao Yamaoka ,  Tomonori Sekiguchi

    IPC分类号： G11C5/06 ,  G11C7/00 ,  H01L23/48 ,  H01L23/52

    CPC分类号： H01L25/0657 ,  G11C5/02 ,  H01L25/18 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599

    摘要： The need for mediation operation is eliminated by adoption of a connection topology in which a circuit for executing one transmission (TR—00T), and a circuit for executing a plurality of receptions (TR—10R, TR—20R, TR—30R) are connected to one penetration-electrode group (for example, TSVGL—0). In order to implement the connection topology even in the case of piling up a plurality of LSIs one after another, in particular, a programmable memory element for designating respective penetration-electrode ports for use in transmit, or for us in receive, and address allocation of the respective penetration-electrode ports is mounted in stacked LSIs.

    摘要翻译： 通过采用其中执行一次发送的电路（TR-00T）和用于执行多个接收（TR-10R，TR-20R，TR-30R）的电路的连接拓扑结构来消除对中介操作的需要 连接到一个穿透电极组（例如，TSVGL-0）。 为了实现连接拓扑，即使在堆叠多个LSI的情况下，尤其是用于指定用于发送的各个穿透电极端口或用于接收的可编程存储器元件，以及地址分配 各个贯通电极端口安装在堆叠的LSI中。

    SEMICONDUCTOR DEVICE
    49.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20120162836A1

    公开(公告)日：2012-06-28

    申请号：US13332861

    申请日：2011-12-21

    申请人： Futoshi FURUTA ,  Kenichi Osada

    发明人： Futoshi FURUTA ,  Kenichi Osada

    IPC分类号： H02H9/04 ,  H03K17/693

    CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L23/62 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15311 ,  H02H9/046

    摘要： In a stacked chip system, an IO circuit connected to a TSV pad for IO and a switch circuit constitute an IO channel in each chip, the IO channels as many as the maximum scheduled number of stacks are coupled together and connected to constitute an IO group, and the chip has one or more such IO groups. Each TSV pad for IO is connected with a through via to an IO terminal at the same position in a chip of another layer. On an interposer, if the actual number of stacks is less than the maximum scheduled number of stacks, connection pads for IO in adjacent IO groups on the interposer are connected via a conductor.

    摘要翻译： 在堆叠式芯片系统中，连接到用于IO的TSV焊盘和开关电路的IO电路构成每个芯片中的IO通道，与最大预定堆栈数量一样多的IO通道耦合在一起并连接以构成IO组 ，并且芯片具有一个或多个这样的IO组。 用于IO的每个TSV焊盘与通孔连接到另一层的芯片中相同位置处的IO端子。 在插入器上，如果堆栈的实际数量小于堆栈的最大预定数量，则插入器上相邻IO组中IO的连接焊盘将通过导线连接。