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180 条记录 (耗时 0.029 秒)

    FIELD EFFECT TRANSISTORS WITH LOW K SIDEWALL SPACERS AND METHODS OF FABRICATING SAME
    43.
    发明申请
    FIELD EFFECT TRANSISTORS WITH LOW K SIDEWALL SPACERS AND METHODS OF FABRICATING SAME 失效
    具有低K面积间距的场效应晶体管及其制造方法

    公开(公告)号：US20120126342A1

    公开(公告)日：2012-05-24

    申请号：US12948805

    申请日：2010-11-18

    申请人： Kangguo Cheng ,  Louis Lu-Chen Hsu ,  William R. Tonti

    发明人： Kangguo Cheng ,  Louis Lu-Chen Hsu ,  William R. Tonti

    IPC分类号： H01L29/772 ,  H01L21/336

    CPC分类号： H01L29/4983 ,  H01L21/26586 ,  H01L21/268 ,  H01L29/665

    摘要： Field effect transistors and method for forming filed effect transistors. The field effect transistors including: a gate dielectric on a channel region in a semiconductor substrate; a gate electrode on the gate dielectric; respective source/drains in the substrate on opposite sides of the channel region; sidewall spacers on opposite sides of the gate electrode proximate to the source/drains; and wherein the sidewall spacers comprise a material having a dielectric constant lower than that of silicon dioxide and capable of absorbing laser radiation.

    摘要翻译： 场效应晶体管和形成场效应晶体管的方法。 场效应晶体管包括：半导体衬底中的沟道区上的栅极电介质; 栅电极上的栅电极; 在沟道区域的相对侧上的衬底中的相应源极/漏极; 靠近源极/漏极的栅电极的相对侧上的侧壁间隔物; 并且其中所述侧壁间隔物包括介电常数低于二氧化硅的介电常数且能够吸收激光辐射的材料。

    Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates
    44.
    发明授权
    Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates 失效
    用于形成这种混合取向基板的混合取向基板和晶体压印方法

    公开(公告)号：US07875960B2

    公开(公告)日：2011-01-25

    申请号：US12182560

    申请日：2008-07-30

    申请人： Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  William Robert Tonti

    发明人： Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  William Robert Tonti

    IPC分类号： H01L29/04

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L29/045

    摘要： A semiconductor structure with an insulating layer on a silicon substrate, a plurality of electrically-isolated silicon-on-insulator (SOI) regions separated from the substrate by the insulating layer, and a plurality of electrically-isolated silicon bulk regions extending through the insulating layer to the substrate. Each of one number of the SOI regions is oriented with a first crystal orientation and each of another number of the SOI regions is oriented with a second crystal orientation that differs from the first crystal orientation. The bulk silicon regions are each oriented with a third crystal orientation. Damascene or imprinting methods of forming the SOI regions and bulk silicon regions are also provided.

    摘要翻译： 一种在硅衬底上具有绝缘层的半导体结构，通过绝缘层从衬底分离出的多个电隔离绝缘体上硅（SOI）区域，以及延伸穿过绝缘体的多个电隔离硅体区域 层到基底。 SOI区域中的每一个以第一晶体取向取向，并且另外数量的SOI区域中的每一个以与第一晶体取向不同的第二晶体取向取向。 体硅区域各自定向为具有第三晶体取向。 还提供了形成SOI区域和体硅区域的镶嵌或印记方法。

    ELECTRONIC FUSES IN SEMICONDUCTOR INTEGRATED CIRCUITS
    45.
    发明申请
    ELECTRONIC FUSES IN SEMICONDUCTOR INTEGRATED CIRCUITS 有权
    半导体集成电路中的电子熔丝

    公开(公告)号：US20100320563A1

    公开(公告)日：2010-12-23

    申请号：US12870921

    申请日：2010-08-30

    申请人： Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  William Robert Tonti ,  Chih-Chao Yang

    发明人： Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  William Robert Tonti ,  Chih-Chao Yang

    IPC分类号： H01L23/525

    CPC分类号： H01L23/5256 ,  H01L21/76807 ,  H01L21/76892 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

    摘要： A structure. The structure includes: a substrate; a first electrode in the substrate; a dielectric layer on top of the substrate and the electrode; a second dielectric layer on the first dielectric layer, said second dielectric layer comprising a second dielectric material; a fuse element buried in the first dielectric layer, wherein the fuse element (i) physically separates, (ii) is in direct physical contact with both, and (iii) is sandwiched between a first region and a second region of the dielectric layer; and a second electrode on top of the fuse element, wherein the first electrode and the second electrode are electrically coupled to each other through the fuse element.

    摘要翻译： 一个结构。 该结构包括：基底; 衬底中的第一电极; 在所述基板和所述电极的顶部上的介电层; 在所述第一介电层上的第二电介质层，所述第二电介质层包括第二电介质材料; 埋入第一介电层中的熔丝元件，其中熔融元件（i）物理分离，（ii）与二者直接物理接触，（iii）被夹在介电层的第一区域和第二区域之间; 以及在所述熔丝元件的顶部上的第二电极，其中所述第一电极和所述第二电极通过所述熔丝元件彼此电耦合。

    Semiconductor device structures with reduced junction capacitance and drain induced barrier lowering and methods for fabricating such device structures and for fabricating a semiconductor-on-insulator substrate
    47.
    发明授权
    Semiconductor device structures with reduced junction capacitance and drain induced barrier lowering and methods for fabricating such device structures and for fabricating a semiconductor-on-insulator substrate 失效
    具有减小的结电容和漏极引起的屏障降低的半导体器件结构以及用于制造这种器件结构和用于制造绝缘体上半导体衬底的方法

    公开(公告)号：US07659178B2

    公开(公告)日：2010-02-09

    申请号：US11379655

    申请日：2006-04-21

    申请人： Kangguo Cheng ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  Haining Yang

    发明人： Kangguo Cheng ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  Haining Yang

    IPC分类号： H01L21/311 ,  H01L21/3115

    CPC分类号： H01L29/66545 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78603 ,  Y10S438/96

    摘要： Semiconductor device structures with reduced junction capacitance and drain induced barrier lowering, methods for fabricating such device structures, and methods for forming a semiconductor-on-insulator substrate. The semiconductor structure comprises a semiconductor layer and a dielectric layer disposed between the semiconductor layer and the substrate. The dielectric layer includes a first dielectric region with a first dielectric constant and a second dielectric region with a second dielectric constant that is greater than the first dielectric constant. In one embodiment, the dielectric constant of the first dielectric region may be less than about 3.9 and the dielectric constant of the second dielectric region may be greater than about ten (10). The semiconductor-on-insulator substrate comprises a semiconductor layer separated from a bulk layer by an insulator layer of a high-dielectric constant material. The fabrication methods comprise modifying a region of the dielectric layer to have a lower dielectric constant.

    摘要翻译： 具有减小的结电容和漏极引发的屏障降低的半导体器件结构，用于制造这种器件结构的方法以及用于形成绝缘体上半导体衬底的方法。 半导体结构包括半导体层和设置在半导体层和衬底之间的电介质层。 电介质层包括具有第一介电常数的第一电介质区域和具有大于第一介电常数的第二介电常数的第二电介质区域。 在一个实施例中，第一电介质区域的介电常数可以小于约3.9，并且第二电介质区域的介电常数可以大于约十（10）。 绝缘体上半导体衬底包括通过高介电常数材料的绝缘体层与本体层分离的半导体层。 制造方法包括修改介电层的区域以具有较低的介电常数。

    Electronic fuse with conformal fuse element formed over a freestanding dielectric spacer
    48.
    发明授权
    Electronic fuse with conformal fuse element formed over a freestanding dielectric spacer 失效
    具有保形熔丝元件的电子保险丝，形成在独立电介质垫片上

    公开(公告)号：US07545253B2

    公开(公告)日：2009-06-09

    申请号：US12128100

    申请日：2008-05-28

    申请人： Louis Lu-Chen Hsu ,  Jack A. Mandelman ,  William R. Tonti ,  Chih-Chao Yang

    发明人： Louis Lu-Chen Hsu ,  Jack A. Mandelman ,  William R. Tonti ,  Chih-Chao Yang

    IPC分类号： H01H85/08 ,  H01L23/62

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  Y10T29/49107 ,  H01L2924/00

    摘要： An electronic fuse for an integrated circuit and a method of fabrication thereof are presented. The electronic fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The fuse element has a convex upper surface and a lower surface with a radius of curvature at a smallest surface area of curvature less than or equal to 100 nanometers. Fabricating the electronic fuse includes forming an at least partially freestanding dielectric spacer above a supporting structure, and then conformably forming the fuse element of the fuse over at least a portion of the freestanding dielectric spacer, with the fuse element characterized as noted above. The dielectric spacer may remain in place as a thermally insulating layer underneath the fuse element, or may be removed to form a void underneath the fuse element.

    摘要翻译： 本发明提供一种用于集成电路的电子熔断器及其制造方法。 电子熔断器具有由熔丝元件互连的第一端子部分和第二端子部分。 保险丝元件具有凸起的上表面和具有小于或等于100纳米的曲率的最小表面积的曲率半径的下表面。 制造电子熔断器包括在支撑结构之上形成至少部分独立的介电隔离物，然后在独立电介质隔离物的至少一部分上顺应地形成熔丝的熔丝元件，其中熔丝元件的特征如上所述。 电介质间隔物可以保留在熔丝元件下面的绝热层的适当位置，或者可以被去除以在熔丝元件下面形成空隙。

    Pillar P-i-n semiconductor diodes
    49.
    发明授权
    Pillar P-i-n semiconductor diodes 失效
    支柱P-i-n半导体二极管

    公开(公告)号：US07525170B2

    公开(公告)日：2009-04-28

    申请号：US11538557

    申请日：2006-10-04

    申请人： Louis Lu-Chen Hsu ,  Jack A. Mandelman ,  Kangguo Cheng

    发明人： Louis Lu-Chen Hsu ,  Jack A. Mandelman ,  Kangguo Cheng

    IPC分类号： H01L31/058

    CPC分类号： H01L31/035281 ,  H01L27/1446 ,  H01L31/022408 ,  H01L31/022466 ,  H01L31/028 ,  H01L31/1804 ,  H01L31/1884 ,  Y02E10/547 ,  Y02P70/521

    摘要： An arrangement of pillar shaped p-i-n diodes having a high aspect ration are formed on a semiconductor substrate. Each device is formed by an intrinsic or lightly doped region (i-region) positioned between a P+ region and an N+ region at each end of the pillar. The arrangement of pillar p-i-n diodes is embedded in an optical transparent medium. For a given surface area, more light energy is absorbed by the pillar arrangement of p-i-n diodes than by conventional planar p-i-n diodes. The pillar p-i-n diodes are preferably configured in an array formation to enable photons reflected from one pillar p-i-n diode to be captured and absorbed by another p-i-n diode adjacent to the first one, thereby optimizing the efficiency of energy conversion.

    摘要翻译： 在半导体衬底上形成具有高纵横比的柱状p-i-n二极管的布置。 每个器件由位于柱的每个端部处的P +区域和N +区域之间的本征或轻掺杂区域（i区域）形成。 柱p-i-n二极管的布置被嵌入在光学透明介质中。 对于给定的表面积，p-i-n二极管的支柱排列比常规平面p-i-n二极管吸收更多的光能。 支柱p-i-n二极管优选地被配置成阵列形成，以使得从一个柱p-i-n二极管反射的光子被与第一个p-i-n二极管相邻的另一个p-i-n二极管捕获和吸收，从而优化了能量转换的效率。