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    Semiconductor devices and methods of fabrication
    43.
    发明授权
    Semiconductor devices and methods of fabrication 有权

    公开(公告)号：US10608004B2

    公开(公告)日：2020-03-31

    申请号：US16028111

    申请日：2018-07-05

    Applicant: Micron Technology, Inc.

    Inventor： Hongbin Zhu ,  Zhenyu Lu ,  Gordon Haller ,  Jie Sun ,  Randy J. Koval ,  John Hopkins

    IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/10 ,  H01L29/51 ,  H01L21/311 ,  H01L27/1157 ,  H01L21/28 ,  H01L29/66

    Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

    Drain select gate formation methods and apparatus
    47.
    发明授权
    Drain select gate formation methods and apparatus 有权

    公开(公告)号：US09842847B2

    公开(公告)日：2017-12-12

    申请号：US14619243

    申请日：2015-02-11

    Applicant: Micron Technology, Inc.

    Inventor： Hongbin Zhu ,  Lijing Gou ,  Gordon Haller ,  Luan C. Tran

    IPC: H01L27/1156 ,  H01L27/11556 ,  H01L27/11582

    CPC classification number: H01L27/11556 ,  H01L27/11582

    Abstract: Some embodiments include a string of charge storage devices formed along a vertical channel of semiconductor material; a gate region of a drain select gate (SGD) transistor, the gate region at least partially surrounding the vertical channel; a dielectric barrier formed in the gate region; a first isolation layer formed above the gate region and the dielectric barrier; a drain region of the SGD transistor formed above the vertical channel; and a second isolation layer formed above the first isolation layer and the drain region, wherein the second isolation layer includes a conductive contact in electrical contact with the drain region of the SGD transistor. Additional apparatus and methods are disclosed.

    METHODS AND APPARATUSES HAVING MEMORY CELLS INCLUDING A MONOLITHIC SEMICONDUCTOR CHANNEL
    48.
    发明申请
    METHODS AND APPARATUSES HAVING MEMORY CELLS INCLUDING A MONOLITHIC SEMICONDUCTOR CHANNEL 有权
    具有包含单个半导体通道的记忆细胞的方法和装置

    公开(公告)号：US20150123189A1

    公开(公告)日：2015-05-07

    申请号：US14069574

    申请日：2013-11-01

    Applicant: Micron Technology, Inc.

    Inventor： Jie Sun ,  Zhenyu Lu ,  Roger W. Lindsay ,  Brian Cleereman ,  John Hopkins ,  Hongbin Zhu ,  Fatma Arzum Simsek-Ege ,  Prasanna Srinivasan ,  Purnima Narayanan

    IPC: H01L27/115

    CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/66825 ,  H01L29/7889

    Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.

    Abstract translation: 公开了形成一串存储单元的方法，具有一串存储单元的装置和系统。 用于形成一串存储单元的一种这样的方法在衬底上形成源材料。 可以在源材料上形成封盖材料。 可以在封盖材料之上形成选择栅极材料。 多个电荷存储结构可以在选择栅极材料上以多个交替层级的控制栅极和绝缘体材料形成。 可以通过控制栅极和绝缘体材料，选择栅极材料和封盖材料的多个交替层级形成第一开口。 通道材料可以沿着第一开口的侧壁形成。 通道材料的厚度小于第一开口的宽度，使得第二开口由半导体沟道材料形成。

    Semiconductor devices including WiSX
    49.
    发明授权
    Semiconductor devices including WiSX 有权
    半导体器件包括WiSX

    公开(公告)号：US08963156B2

    公开(公告)日：2015-02-24

    申请号：US13774599

    申请日：2013-02-22

    Applicant: Micron Technology, Inc.

    Inventor： Hongbin Zhu ,  Gordon Haller ,  Paul D. Long

    IPC: H01L29/76 ,  H01L31/036 ,  H01L31/112 ,  H01L21/768 ,  H01L23/522

    CPC classification number: H01L21/823412 ,  H01L23/5226 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/66787 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon formed on a substrate. Such a semiconductor device may further include at least one opening having a high aspect ratio and extending into the stack structure to a level adjacent the substrate, a first poly-silicon channel formed in a lower portion of the opening adjacent the substrate, a second poly-silicon channel formed in an upper portion of the opening, and WSiX material disposed between the first poly-silicon channel and the second poly-silicon channel in the opening. The WSiX material is adjacent to the substrate, and can be used as an etch-landing layer and a conductive contact to contact both the first poly-silicon channel and the second poly-silicon channel in the opening. Other embodiments include methods of making semiconductor devices.

    Abstract translation: 一些实施例包括具有堆叠结构的半导体器件，该堆叠结构包括形成在衬底上的多个交替层的介电材料和多晶硅。 这样的半导体器件还可以包括至少一个具有高纵横比并且延伸到堆叠结构中的开口至与衬底相邻的水平，形成在邻近衬底的开口下部的第一多晶硅沟道，第二聚硅 - 硅沟道，以及设置在开口中的第一多晶硅沟道和第二多晶硅沟道之间的WSiX材料。 WSiX材料与衬底相邻，并且可以用作蚀刻着色层和导电触点，以在开口中接触第一多晶硅沟道和第二多晶硅沟道。 其他实施例包括制造半导体器件的方法。

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