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    Method, electronic device and controller for recovering memory array
    42.
    发明授权
    Method, electronic device and controller for recovering memory array 有权
    方法，用于恢复存储器阵列的电子设备和控制器

    公开(公告)号：US09396806B2

    公开(公告)日：2016-07-19

    申请号：US14182314

    申请日：2014-02-18

    Applicant: Macronix International Co., Ltd.

    Inventor： Kuen-Long Chang ,  Nai-Ping Kuo ,  Ken-Hui Chen ,  Chao-Hsin Lin

    IPC: G11C29/00 ,  G11C16/34

    CPC classification number: G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34 ,  G11C16/3418

    Abstract: A method, an electronic device and a controller for recovering an array of memory cells are provided. The method comprises the following steps. Whether a recovery control signal is received or not is determined. A retention checking procedure is executed for identifying whether a threshold voltage distribution of at least one bit of the memory cells in high threshold state is shifted or not, if the recovery control signal is received. A retention writing procedure is executed on the memory cells, if the memory cells in high threshold state do not pass the retention checking procedure.

    Abstract translation: 提供了一种用于恢复存储器单元阵列的方法，电子设备和控制器。 该方法包括以下步骤。 确定是否接收到恢复控制信号。 如果接收到恢复控制信号，则执行保持检查程序，用于识别高阈值状态下的存储器单元的至少一位的阈值电压分布是否移位。 如果高阈值状态的存储单元不通过保留检查程序，则在存储器单元上执行保留写入过程。

    METHOD, ELECTRONIC DEVICE AND CONTROLLER FOR RECOVERING ARRAY OF MEMORY CELLS
    45.
    发明申请
    METHOD, ELECTRONIC DEVICE AND CONTROLLER FOR RECOVERING ARRAY OF MEMORY CELLS 有权
    用于恢复记忆体阵列的方法，电子装置和控制器

    公开(公告)号：US20150143171A1

    公开(公告)日：2015-05-21

    申请号：US14182314

    申请日：2014-02-18

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Kuen-Long Chang ,  Nai-Ping Kuo ,  Ken-Hui Chen ,  Chao-Hsin Lin

    IPC: G06F11/14

    CPC classification number: G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34 ,  G11C16/3418

    Abstract: A method, an electronic device and a controller for recovering an array of memory cells are provided. The method comprises the following steps. Whether a recovery control signal is received or not is determined. A retention checking procedure is executed for identifying whether a threshold voltage distribution of at least one bit of the memory cells in high threshold state is shifted or not, if the recovery control signal is received. A retention writing procedure is executed on the memory cells, if the memory cells in high threshold state do not pass the retention checking procedure.

    Abstract translation: 提供了一种用于恢复存储器单元阵列的方法，电子设备和控制器。 该方法包括以下步骤。 确定是否接收到恢复控制信号。 如果接收到恢复控制信号，则执行保持检查程序，用于识别高阈值状态下的存储器单元的至少一位的阈值电压分布是否移位。 如果高阈值状态的存储单元不通过保留检查程序，则在存储器单元上执行保留写入过程。

    METHOD AND SYSTEM FOR ENHANCED PERFORMANCE IN SERIAL PERIPHERAL INTERFACE
    47.
    发明申请
    METHOD AND SYSTEM FOR ENHANCED PERFORMANCE IN SERIAL PERIPHERAL INTERFACE 审中-公开
    串行外围接口中增强性能的方法和系统

    公开(公告)号：US20140237207A1

    公开(公告)日：2014-08-21

    申请号：US14264013

    申请日：2014-04-28

    Applicant: Macronix International Co., Ltd.

    Inventor： CHUNG-HSIUNG HUNG ,  Kuen-Long Chang ,  Chia-He Liu

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G06F12/00 ,  G06F13/4286

    Abstract: A method of conducting an operation in an integrated circuit having a plurality of memory cells includes receiving an operating command for the memory cells and receiving a first address segment associated with the memory cells in at least one clock cycle after receiving the operating command. The method further includes receiving a first performance enhancement indicator in at least one clock cycle after ending the first address segment while before starting to transfer data, for determining whether an enhanced operation is to be performed.

    Abstract translation: 在具有多个存储单元的集成电路中执行操作的方法包括在接收到操作命令之后的至少一个时钟周期中接收用于存储器单元的操作命令并接收与存储器单元相关联的第一地址段。 该方法还包括在开始传送数据之前，在结束第一地址段之后的至少一个时钟周期内接收第一性能增强指示符，以确定是否执行增强的操作。

    Method and system for enhanced performance in serial peripheral interface
    48.
    发明授权
    Method and system for enhanced performance in serial peripheral interface 有权
    串行外设接口提高性能的方法和系统

    公开(公告)号：US08738849B2

    公开(公告)日：2014-05-27

    申请号：US13686917

    申请日：2012-11-28

    Applicant: Macronix International Co., Ltd.

    Inventor： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Chia-He Liu

    IPC: G06F12/00

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G06F12/00 ,  G06F13/4286

    Abstract: A method of conducting an operation in an integrated circuit having a plurality of memory cells includes receiving an operating command for the memory cells and receiving a first address segment associated with the memory cells in at least one clock cycle after receiving the operating command. The method further includes receiving a first performance enhancement indicator in at least one clock cycle after ending the first address segment while before starting to transfer data, for determining whether an enhanced operation is to be performed.

    Abstract translation: 在具有多个存储单元的集成电路中执行操作的方法包括在接收到操作命令之后的至少一个时钟周期中接收用于存储器单元的操作命令并接收与存储器单元相关联的第一地址段。 该方法还包括在开始传送数据之前，在结束第一地址段之后的至少一个时钟周期内接收第一性能增强指示符，以确定是否执行增强的操作。

    Memory apparatus and associated control method for reducing erase disturb of non-volatile memory
    49.
    发明授权
    Memory apparatus and associated control method for reducing erase disturb of non-volatile memory 有权

    公开(公告)号：US11631464B2

    公开(公告)日：2023-04-18

    申请号：US17178313

    申请日：2021-02-18

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Su-Chueh Lo ,  Kuen-Long Chang

    IPC: G11C16/16 ,  G11C16/30 ,  G11C16/34 ,  G11C16/26

    Abstract: A memory apparatus and a control method are provided. The memory apparatus includes a non-volatile memory array having plural memory groups, and the control method is applied to the non-volatile memory array. The memory groups jointly share a first well, and the control method is applied to the non-volatile memory array. A first memory group among the memory groups is erased according to a first erase command after the memory apparatus is power-on, and a first amount of the memory groups are recovered in a first erase-recover procedure after the first memory group is erased. A second memory group among the memory groups is erased according to a second erase command after the first erase-recover procedure, and a second amount of the memory groups are recovered in a second erase-recover procedure after the second memory group is erased. The first amount is greater than the second amount.

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