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    Polymeric-shaped article
    41.
    发明授权
    Polymeric-shaped article 失效
    聚合物制品

    公开(公告)号：US4190689A

    公开(公告)日：1980-02-26

    申请号：US878837

    申请日：1978-02-17

    申请人： Saburo Fujita ,  Masahiko Motegi ,  Satoru Okamoto ,  Atsuhiko Soda ,  Masakazu Inoue

    发明人： Saburo Fujita ,  Masahiko Motegi ,  Satoru Okamoto ,  Atsuhiko Soda ,  Masakazu Inoue

    IPC分类号： C08J7/06 ,  B32B5/16

    CPC分类号： C08J7/06 ,  Y10T428/24893 ,  Y10T428/24901 ,  Y10T428/24909 ,  Y10T428/256 ,  Y10T428/31

    摘要： A polymeric-shaped article for use as film such as microfilm, overhead projector film, reprographic film, layout base, etc., and for insulating capacitors, which has excellent transparent, slippery and dielectric properties, and the process for realizing the same, the polymeric-shaped article having a polar surface such as polyester, polyamide, polyolefins, polyimide, polyvinyl alcohol, polyethylene terephthalate or polyethylene-2,6-naphthalate, to which is bonded a multiplicity of nodules of TiO.sub.2, each nodule having a diameter in the range of from about 0.01 to about 10 .mu.m, a height or thickness in the range of from about 0.01 to about 0.5 .mu.m, and an area ratio of TiO.sub.2 to total surface of from about 0.01 to about 50%; and the process being that of exposing at least one side of the surface of the article to water vapor and bringing a tetrafunctional titanium compound such as TiCl.sub.4, tetraethyltitanate, tetraisopropyltitanate, tetra-n-butyltitanate or mixture thereof, into contact with the surface, the processing temperature being at least greater than 30.degree. C.

    摘要翻译： 用作薄膜的聚合物制品，例如微缩胶片，高架投影仪膜，复印膜，布局基底等，以及具有优异的透明，光滑和介电性能的绝缘电容器及其实现方法 具有极性表面的聚合物制品，例如聚酯，聚酰胺，聚烯烃，聚酰亚胺，聚乙烯醇，聚对苯二甲酸乙二醇酯或聚2,6-萘二甲酸乙二醇酯，其中结合了多个结节TiO 2，每个结节具有直径在 约0.01至约10μm的范围，高度或厚度在约0.01至约0.5μm范围内，并且TiO 2与总表面的面积比为约0.01至约50％; 并且该方法是使制品的表面的至少一侧暴露于水蒸汽并且使四钛官能化钛如钛酸四丁酯，钛酸四乙酯，钛酸四异丙酯，钛酸四异丁酯或其混合物与表面接触， 处理温度至少大于30℃

    LAMINATED COIL COMPONENT
    42.
    发明申请
    LAMINATED COIL COMPONENT 审中-公开
    层压线圈组件

    公开(公告)号：US20140145816A1

    公开(公告)日：2014-05-29

    申请号：US14131948

    申请日：2012-08-20

    申请人： Takahiro Sato ,  Yuya Ishima ,  Shusaku Umemoto ,  Takashi Suzuki ,  Satoru Okamoto ,  Yoshikazu Sakaguchi

    发明人： Takahiro Sato ,  Yuya Ishima ,  Shusaku Umemoto ,  Takashi Suzuki ,  Satoru Okamoto ,  Yoshikazu Sakaguchi

    IPC分类号： H01F5/06

    CPC分类号： H01F5/06 ,  H01F17/0013 ,  H01F2017/004

    摘要： A laminated coil component includes an element assembly formed by laminating a plurality of insulation layers and a coil unit formed inside the element assembly by a plurality of coil conductors. The element assembly includes a coil unit arrangement layer which has the coil unit arranged therein, and at least a pair of shape retention layers which is provided to have the coil unit arrangement layer interposed therebetween to retain a shape of the coil unit arrangement layer. The shape retention layer is made from glass-ceramic containing SrO, and a softening point of the coil unit arrangement layer is lower than a softening point or a melting point of the shape retention layer.

    摘要翻译： 层叠线圈部件包括通过层叠多个绝缘层而形成的元件组件和通过多个线圈导体在元件组件内形成的线圈单元。 元件组件包括线圈单元布置层，线圈单元布置在其中，并且至少一对形状保持层设置成使线圈单元布置层插入其间以保持线圈单元布置层的形状。 形状保持层由含有SrO的玻璃陶瓷制成，线圈单元配置层的软化点低于形状保持层的软化点或熔点。

    LAMINATED COIL COMPONENT
    43.
    发明申请
    LAMINATED COIL COMPONENT 有权
    层压线圈组件

    公开(公告)号：US20140118100A1

    公开(公告)日：2014-05-01

    申请号：US14125745

    申请日：2012-08-20

    申请人： Takahiro Sato ,  Yuya ISHIMA ,  Shusaku Umemoto ,  Takashi Suzuki ,  Satoru Okamoto ,  Yoshikazu Sakaguchi

    发明人： Takahiro Sato ,  Yuya ISHIMA ,  Shusaku Umemoto ,  Takashi Suzuki ,  Satoru Okamoto ,  Yoshikazu Sakaguchi

    IPC分类号： H01F5/00

    CPC分类号： H01F5/003 ,  H01F17/0013 ,  H01F41/042

    摘要： In the laminated coil component, the grain diameter of the coil conductors is 10 μm to 22 μm after baking is completed. When the grain diameter of the coil conductors is set to be 10 μm or larger after baking is completed, surface roughness of the coil conductors can be reduced to such an extent that a satisfactory Q value can be obtained at a high frequency. In addition, when the grain diameter of the coil conductors is set to be 22 μm or smaller after baking is completed, metal of the coil conductors can be refrained from being rapidly melted down during baking. Accordingly, a high Q value can be obtained while a high quality is ensured.

    摘要翻译： 在层叠线圈部件中，线圈导体的粒径在烘烤完成后为10μm〜22μm。 当线圈导体的粒径在烘烤完成之后设定为10μm以上时，线圈导体的表面粗糙度可以降低到能够以高频获得令人满意的Q值的程度。 此外，当烘烤完成后，当线圈导体的粒径设定为22μm以下时，可以防止线圈导体的金属在烘烤时快速熔化。 因此，可以在确保高质量的同时获得高Q值。

    Method of manufacturing a semiconductor device
    44.
    发明授权
    Method of manufacturing a semiconductor device 有权

    公开(公告)号：US08597427B2

    公开(公告)日：2013-12-03

    申请号：US12201546

    申请日：2008-08-29

    申请人： Satoru Okamoto

    发明人： Satoru Okamoto

    IPC分类号： C30B21/02

    CPC分类号： H01L27/127 ,  H01L27/1214 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78675 ,  H01L2029/7863

    摘要： A semiconductor device is provided which is constituted by semiconductor devices including a thin film transistor with a GOLD structure, the GOLD structure thin film transistor being such that: a semiconductor layer, a gate insulating film, and a gate electrode are formed in lamination from the side closer to a substrate; the gate electrode is constituted of a first-layer gate electrode and a second-layer gate electrode shorter in the size than the first-layer gate electrode; the first-layer gate electrode corresponding to the region exposed from the second-layer gate electrode is formed into a tapered shape so as to be thinner toward the end portion; a first impurity region is formed in the semiconductor layer corresponding to the region with the tapered shape; and a second impurity region having the same conductivity as the first impurity region is formed in the semiconductor layer corresponding to the outside of the first-layer gate electrode, which is characterized in that a dry etching process consisting of one step or two steps is applied to the formation of the gate electrode.

    Dry Etching Agent and Dry Etching Method Using the Same
    46.
    发明申请
    Dry Etching Agent and Dry Etching Method Using the Same 有权
    干蚀刻剂和干法蚀刻方法

    公开(公告)号：US20120298911A1

    公开(公告)日：2012-11-29

    申请号：US13576093

    申请日：2011-01-25

    申请人： Yasuo Hibino ,  Tomonori Umezaki ,  Akiou Kikuchi ,  Isamu Mori ,  Satoru Okamoto

    发明人： Yasuo Hibino ,  Tomonori Umezaki ,  Akiou Kikuchi ,  Isamu Mori ,  Satoru Okamoto

    IPC分类号： C09K13/00

    CPC分类号： H01L21/31055 ,  C09K13/00 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/32136

    摘要： A dry etching agent according to the present invention contains (A) a fluorinated propyne represented by the chemical formula: CF3CCX where X is H, F, Cl, Br, I, CH3, CFH2 or CF2H; and either of: (B) at least one kind of gas selected from the group consisting of O2, O3, CO, CO2, COCl2 and COF2; (C) at least one kind of gas selected from the group consisting of F2, NF3, Cl2, Br2, I2 and YFn where Y is Cl, Br or I; and n is an integer of 1 to 5; and (D) at least one kind of gas selected from the group consisting of CF4, CHF3, C2F6, C2F5H, C2F4H2, C3F8, C3F4H2, C3ClF3H and C4F8. This dry etching agent has a small environmental load and a wide process window and can be applied for high-aspect-ratio processing without special operations such as substrate excitation.

    摘要翻译： 根据本发明的干蚀刻剂包含（A）由化学式CF3CCX表示的氟化丙炔，其中X是H，F，Cl，Br，I，CH 3，CFH 2或CF 2 H; 和（B）选自O 2，O 3，CO，CO 2，COCl 2和COF 2中的至少一种气体; （C）选自由F2，NF3，Cl2，Br2，I2和YFn组成的组中的至少一种气体，其中Y是Cl，Br或I; n为1〜5的整数。 和（D）选自CF4，CHF3，C2F6，C2F5H，C2F4H2，C3F8，C3F4H2，C3ClF3H和C4F8中的至少一种气体。 这种干蚀刻剂具有小的环境负荷和宽的工艺窗口，并且可以应用于高纵横比处理，而不需要诸如基板激励的特殊操作。

    Optical node device, network control device, maintenance-staff device, optical network, and 3R relay implementation node decision method
    48.
    发明授权
    Optical node device, network control device, maintenance-staff device, optical network, and 3R relay implementation node decision method 有权
    光节点设备，网络控制设备，维护人员设备，光网络和3R中继实现节点决策方法

    公开(公告)号：US08081881B2

    公开(公告)日：2011-12-20

    申请号：US12417173

    申请日：2009-04-02

    申请人： Eiji Oki ,  Akira Misawa ,  Masaru Katayama ,  Satoru Okamoto

    发明人： Eiji Oki ,  Akira Misawa ,  Masaru Katayama ,  Satoru Okamoto

    IPC分类号： H04B10/00 ,  H04B10/02 ,  H04B10/08 ,  H04B10/20

    CPC分类号： H04J14/0284 ,  H04B10/299 ,  H04J14/0227 ,  H04J14/0246 ,  H04J14/025 ,  H04J14/0256 ,  H04J14/0257 ,  H04J14/0258 ,  H04J14/0267 ,  H04J14/0269 ,  H04L41/12

    摘要： An economical optical network is constituted by effectively using network resources by using the minimum number of, or minimum capacity of 3R repeaters. 3R section information corresponding to topology information on the optical network to which an optical node device itself belongs is stored, and the 3R section information stored is referred so as to autonomously determine whether or not the optical node device itself is an optical node device for implementing the 3R relay when setting an optical path passing through the optical node device itself. Alternatively, when the optical node device itself is a source node, another optical node device for implementing the 3R relay among the other optical node devices through which the optical path from the optical node device itself to the destination node passes is identified, and this identified optical node device is requested to implement the 3R relay when setting an optical path in which the optical node device itself is a source node.

    摘要翻译： 通过使用3R中继器的最小或最小容量有效地使用网络资源来构成经济的光网络。 存储与光节点设备本身所属的光网络上的拓扑信息对应的3R部分信息，并且参考存储的3R部分信息，以便自主地确定光节点设备本身是否是用于实现的光节点设备 当设置通过光节点设备本身的光路时，3R继电器。 或者，当光节点设备本身是源节点时，识别用于在从光节点设备本身到目的地节点通过的光路经过的其他光节点设备中实现3R中继器的另一光节点设备，并且这被识别 要求光节点设备在设置光节点设备本身是源节点的光路时实现3R中继。

    Formation method of single crystal semiconductor layer, formation method of crystalline semiconductor layer, formation method of polycrystalline layer, and method for manufacturing semiconductor device
    49.
    发明授权
    Formation method of single crystal semiconductor layer, formation method of crystalline semiconductor layer, formation method of polycrystalline layer, and method for manufacturing semiconductor device 有权
    单晶半导体层的形成方法，结晶半导体层的形成方法，多晶层的形成方法以及半导体装置的制造方法

    公开(公告)号：US07888242B2

    公开(公告)日：2011-02-15

    申请号：US12257448

    申请日：2008-10-24

    申请人： Koichiro Tanaka ,  Satoru Okamoto

    发明人： Koichiro Tanaka ,  Satoru Okamoto

    IPC分类号： H01L21/20 ,  H01L21/36

    CPC分类号： H01L27/1266 ,  C30B29/06 ,  C30B31/22 ,  C30B33/00 ,  C30B35/00 ,  H01L21/76251 ,  H01L27/1214

    摘要： A method for forming a single crystal semiconductor layer in which a first porous layer and a second porous layer are formed over a single crystal semiconductor ingot, a groove is formed in a part of the second porous layer and a single crystal semiconductor layer is formed over the second porous layer, the single crystal semiconductor ingot is attached onto a large insulating substrate, water jet is directed to the interface between the first porous layer and the second porous layer, and the single crystal semiconductor layer is attached to the large insulating substrate, or a method for forming a crystalline semiconductor layer in which a crystalline semiconductor ingot is irradiated with hydrogen ions to form a hydrogen ion irradiation region in the crystalline semiconductor ingot, the crystalline semiconductor ingot is rolled over the large insulating substrate while being heated, the crystalline semiconductor layer is separated from the hydrogen ion irradiation region, and the crystalline semiconductor layer is attached to the large insulating substrate.

    摘要翻译： 一种形成单晶半导体层的方法，其中第一多孔层和第二多孔层形成在单晶半导体锭上，在第二多孔层的一部分中形成沟槽，并且形成单晶半导体层 将第二多孔层，单晶半导体晶片安装在大的绝缘基板上，将水射流引导到第一多孔层和第二多孔层之间的界面，并且将单晶半导体层附着在大绝缘基板上， 或用于形成结晶半导体层的方法，其中晶体半导体晶锭被氢离子照射以在晶体半导体晶锭中形成氢离子照射区域，晶体半导体晶锭在加热时在大绝缘基板上滚动，晶体 半导体层与氢离子照射区域分离，并产生哭泣 马赛尼半导体层附着在大绝缘基板上。

    Semiconductor device and manufacturing method thereof
    50.
    发明授权
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US07800114B2

    公开(公告)日：2010-09-21

    申请号：US12116384

    申请日：2008-05-07

    申请人： Satoru Okamoto

    发明人： Satoru Okamoto

    IPC分类号： H01L27/14

    CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/1222 ,  H01L27/127 ,  H01L29/78621 ,  H01L2029/7863 ,  Y10S438/978

    摘要： Manufacture of TFTs corresponding to various circuits makes structures thereof complex, which involves a larger number of manufacturing steps. Such an increase in the number of the manufacturing steps leads to a higher manufacturing cost and a lower manufacturing yield. In the invention, a high concentration of impurities is doped by using as masks a tapered resist that is used for the manufacture of a tapered gate electrode, and the tapered gate electrode, and then the tapered gate electrode is etched in the perpendicular direction using the resist as a mask. A semiconductor layer under the thusly removed tapered portion of the gate electrode is doped with a low concentration of impurities.

    摘要翻译： 对应于各种电路的TFT的制造使其结构复杂，其涉及更多的制造步骤。 这种制造步骤数量的增加导致制造成本更高和制造成品率更低。 在本发明中，通过使用用于制造锥形栅电极的锥形抗蚀剂和锥形栅电极，然后使用以下方式在垂直方向上蚀刻锥形栅电极来掺杂高浓度的杂质 抗拒作为面具。 在栅电极的如此去除的锥形部分下方的半导体层掺杂有低浓度的杂质。