公开(公告)号：US09264013B2

公开(公告)日：2016-02-16

申请号：US14019821

申请日：2013-09-06

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Jonghae Kim ,  Daeik Daniel Kim ,  Mario Francisco Velez ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  Robert Paul Mikulka ,  Matthew Michael Nowak

IPC: H03H7/46 ,  H03H3/00

CPC classification number: H03H7/463 ,  H03H3/00 ,  Y10T29/4902

Abstract: Systems for reducing magnetic coupling in integrated circuits (ICs) are disclosed. Related components and methods are also disclosed. The ICs have a plurality of inductors. Each inductor generates a magnetic flux that has a discernible axis. To reduce magnetic coupling between the inductors, the flux axes are designed so as to be non-parallel. In particular, by making the flux axes of the inductors non-parallel to one another, magnetic coupling between the inductors is reduced relative to the situation where the flux axes are parallel. This arrangement may be particularly well suited for use in diplexers having a low pass and a high pass filter.

Abstract translation: 公开了用于减小集成电路（IC）中的磁耦合的系统。 还公开了相关的部件和方法。 IC具有多个电感器。 每个电感器产生具有可辨别轴线的磁通量。 为了减小电感器之间的磁耦合，磁通轴被设计成不平行。 特别地，通过使电感器的磁通轴彼此不平行，相对于磁通轴平行的情况，电感器之间的磁耦合减小。 这种布置可以特别适用于具有低通和高通滤波器的双工器。

公开(公告)号：US20150074433A1

公开(公告)日：2015-03-12

申请号：US14072735

申请日：2013-11-05

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Steven M. Millendorf ,  Xu Guo ,  David M. Jacobson ,  Kangho Lee ,  Seung H. Kang ,  Matthew Michael Nowak

IPC: G06F21/70 ,  G06F1/26

CPC classification number: G06F21/70 ,  G06F1/26 ,  G09C1/00 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1695 ,  G11C17/02 ,  G11C17/14 ,  H04L9/0866 ,  H04L9/3278 ,  H04L2209/12

Abstract: One feature pertains to a method of implementing a physically unclonable function that includes providing an array of metal-insulator-metal (MIM) devices, where the MIM devices are configured to represent a first resistance state or a second resistance state and a plurality of the MIM devices are initially at the first resistance state. The MIM devices have a random breakdown voltage that is greater than a first voltage and less than a second voltage, where the breakdown voltage represents a voltage that causes the MIM devices to transition from the first resistance state to the second resistance state. The method further includes applying a signal line voltage to the MIM devices to cause a portion of the MIM devices to randomly breakdown and transition from the first resistance state to the second resistance state, the signal line voltage greater than the first voltage and less than the second voltage.

Abstract translation: 一个特征涉及实现物理上不可克隆的功能的方法，其包括提供金属 - 绝缘体 - 金属（MIM）器件的阵列，其中MIM器件被配置为表示第一电阻状态或第二电阻状态，并且多个 MIM器件最初处于第一电阻状态。 MIM器件具有大于第一电压且小于第二电压的随机击穿电压，其中击穿电压表示使MIM器件从第一电阻状态转变到第二电阻状态的电压。 该方法还包括向MIM器件施加信号线电压以使MIM器件的一部分随机击穿并从第一电阻状态转变到第二电阻状态，信号线电压大于第一电压并小于 第二电压。

公开(公告)号：US08536678B2

公开(公告)日：2013-09-17

申请号：US13654245

申请日：2012-10-17

Applicant: QUALCOMM Incorporated

Inventor： Matthew Michael Nowak ,  Shiqun Gu

IPC: H01L29/92

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/642 ,  H01L28/60 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2224/05552

Abstract: A method of manufacturing a semiconductor die having a substrate with a front side and a back side includes fabricating openings for through substrate vias on the front side of the semiconductor die. The method also includes depositing a first conductor in the through substrate vias, depositing a dielectric on the first conductor and depositing a second conductor on the dielectric. The method further includes depositing a protective insulator layer on the back side of the substrate covering the through substrate vias.

Abstract translation: 制造具有正面和背面的基板的半导体管芯的制造方法包括：半导体管芯的正面侧的通过基板通路的制造开口。 该方法还包括在通孔基板通孔中沉积第一导体，在第一导体上沉积电介质并在电介质上沉积第二导体。 该方法还包括在覆盖穿过衬底通孔的衬底的背面上沉积保护绝缘体层。

公开(公告)号：US10546852B2

公开(公告)日：2020-01-28

申请号：US15970618

申请日：2018-05-03

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep Dutta ,  Matthew Michael Nowak

IPC: H01L29/22 ,  H01L27/06 ,  H01L27/092 ,  H01L21/8249 ,  H01L29/93 ,  H01L29/205 ,  H01L29/737

Abstract: A semiconductor device comprises a complementary metal oxide semiconductor (CMOS) device and a heterojunction bipolar transistor (HBT) integrated on a single die. The CMOS device may comprise silicon. The HBT may comprise III-V materials. The semiconductor device may be employed in a radio frequency front end (RFFE) module to reduce size and parasitics of the RFFE module and to provide cost and cycle time savings.

公开(公告)号：US10332911B2

公开(公告)日：2019-06-25

申请号：US15380800

申请日：2016-12-15

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Daeik Daniel Kim ,  Matthew Michael Nowak ,  Jonghae Kim ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  David Francis Berdy

IPC: H01L21/84 ,  H01L23/66 ,  H01L27/12 ,  H01L29/10 ,  H01L29/66 ,  H01L21/304 ,  H01L21/306 ,  H01L21/762 ,  H01L21/768 ,  H01L23/498 ,  H01L23/528 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8234

Abstract: An integrated circuit (IC) includes a glass substrate and a buried oxide layer. The IC additionally includes a first semiconductor device coupled to the glass substrate. The first semiconductor device includes a first gate and a first portion of a semiconductive layer coupled to the buried oxide layer. The first gate is located between the glass substrate and the first portion of the semiconductive layer and between the glass substrate and the buried oxide layer. The IC additionally includes a second semiconductor device coupled to the glass substrate. The second semiconductor device includes a second gate and a second portion of the semiconductive layer. The second gate is located between the glass substrate and the second portion of the semiconductive layer. The first portion is discontinuous from the second portion.

公开(公告)号：US10158030B2

公开(公告)日：2018-12-18

申请号：US15431623

申请日：2017-02-13

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Gengming Tao ,  Richard Hammond ,  Ranadeep Dutta ,  Matthew Michael Nowak ,  Francesco Carobolante

IPC: H01L29/93 ,  H01L29/20 ,  H01L29/22 ,  H01L29/47 ,  H01L29/737 ,  H01L29/66 ,  H01L27/06 ,  H01L21/822 ,  H01L23/00 ,  H01L23/66 ,  H03H11/34 ,  H03H11/04

Abstract: A tunable capacitor may include a first terminal having a first semiconductor component with a first polarity. The tunable capacitor may also include a second terminal having a second semiconductor component with a second polarity. The second component may be adjacent to the first semiconductor component. The tunable capacitor may further include a first conductive material electrically coupled to a first depletion region at a first sidewall of the first semiconductor component.

公开(公告)号：US09793164B2

公开(公告)日：2017-10-17

申请号：US14939561

申请日：2015-11-12

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Machkaoutsan ,  Stanley Seungchul Song ,  John Jianhong Zhu ,  Junjing Bao ,  Jeffrey Junhao Xu ,  Mustafa Badaroglu ,  Matthew Michael Nowak ,  Choh Fei Yeap

IPC: G06F17/50 ,  G06F19/00 ,  H01L21/00 ,  H01L23/00 ,  H01L21/768 ,  H01L23/532 ,  H01L21/302 ,  H01L21/461 ,  H01L21/311

CPC classification number: H01L21/76897 ,  G06F17/5068 ,  G06F17/5077 ,  G06F19/00 ,  G06F2217/12 ,  H01L21/302 ,  H01L21/311 ,  H01L21/461 ,  H01L21/76808 ,  H01L21/76816 ,  H01L23/53228

Abstract: Self-aligned metal cut and via for Back-End-Of-Line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices, is disclosed. In this manner, mask placement overlay requirements can be relaxed. This relaxation can be multiples of that allowed by conventional BEOL techniques. This is enabled through application of different fill materials for alternating lines in which a conductor will later be placed. With these different fill materials in place, a print cut and via mask is used, with the mask allowed to overlap other adjacent fill lines to that of the desired line. Etching is then applied that is selective to the desired line but not adjacent lines.

公开(公告)号：US09673275B2

公开(公告)日：2017-06-06

申请号：US14920851

申请日：2015-10-22

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  Niranjan Sunil Mudakatte ,  Jonghae Kim ,  Matthew Michael Nowak

IPC: H01L29/06 ,  H01L29/78 ,  H01L23/48 ,  H01L21/762 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L29/0653 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/76898 ,  H01L21/78 ,  H01L21/823481 ,  H01L23/3128 ,  H01L23/481 ,  H01L29/78

Abstract: Isolated complementary metal-oxide semiconductor (CMOS) devices for radio-frequency (RF) circuits are disclosed. In some aspects, an RF circuit includes CMOS devices, a silicon substrate having doped regions that define the CMOS devices, and a trench through the silicon substrate. The trench through the silicon substrate forms a continuous channel around the doped regions of one of the CMOS devices to electrically isolate the CMOS device from other CMOS devices embodied on the silicon substrate. By so doing, performance characteristics of the CMOS device, such as linearity and signal isolation, may be improved over those of conventional CMOS devices (e.g., bulk CMOS).

公开(公告)号：US20170098663A1

公开(公告)日：2017-04-06

申请号：US15380800

申请日：2016-12-15

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Daeik Daniel Kim ,  Matthew Michael Nowak ,  Jonghae Kim ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  David Francis Berdy

IPC: H01L27/12 ,  H01L23/528 ,  H01L21/768 ,  H01L21/84 ,  H01L21/762 ,  H01L29/10 ,  H01L27/092

CPC classification number: H01L27/1203 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/76251 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/49894 ,  H01L23/528 ,  H01L23/66 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1207 ,  H01L27/1222 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1266 ,  H01L29/1087 ,  H01L29/66772

Abstract: An integrated circuit (IC) includes a glass substrate and a buried oxide layer. The IC additionally includes a first semiconductor device coupled to the glass substrate. The first semiconductor device includes a first gate and a first portion of a semiconductive layer coupled to the buried oxide layer. The first gate is located between the glass substrate and the first portion of the semiconductive layer and between the glass substrate and the buried oxide layer. The IC additionally includes a second semiconductor device coupled to the glass substrate. The second semiconductor device includes a second gate and a second portion of the semiconductive layer. The second gate is located between the glass substrate and the second portion of the semiconductive layer. The first portion is discontinuous from the second portion.

公开(公告)号：US09478541B2

公开(公告)日：2016-10-25

申请号：US14480156

申请日：2014-09-08

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Kern Rim ,  Jeffrey Junhao Xu ,  Matthew Michael Nowak ,  Choh Fei Yeap ,  Roawen Chen

IPC: G06F17/50 ,  H01L27/088 ,  G03F7/00 ,  H01L21/8234 ,  H01L27/02

CPC classification number: H01L27/0886 ,  G03F7/00 ,  G06F17/5068 ,  H01L21/823431 ,  H01L27/0207

Abstract: A method for half-node scaling a circuit layout in accordance with an aspect of the present disclosure includes vertical devices on a die. The method includes reducing a fin pitch and a gate pitch of the vertical devices on the die. The method also includes scaling a wavelength to define at least one reduced area geometric pattern of the circuit layout.

Abstract translation: 根据本公开的一个方面的用于半节点缩放电路布局的方法包括裸片上的垂直设备。 该方法包括降低管芯上的垂直装置的翅片间距和栅极间距。 该方法还包括缩放波长以限定电路布局的至少一个缩小区域几何图案。