公开(公告)号：US20140258768A1

公开(公告)日：2014-09-11

申请号：US14351456

申请日：2012-10-11

Applicant: RAMBUS INC.

Inventor： Yu Chang ,  Lei Luo ,  Kyung Suk Oh

IPC: G06F1/32

CPC classification number: G06F1/32 ,  G06F1/30 ,  G06F1/3203 ,  G06F1/3237 ,  Y02D10/128

Abstract: Disclosed embodiments relate to a system that changes transmitter and/or receiver settings to deal with reliability issues caused by a predetermined event, such as a change in a power state or a clock start event. One embodiment uses a first setting while operating a transmitter during a normal operating mode, and a second setting while operating the transmitter during a transient period following the predetermined event. A second embodiment uses similar first and second settings in a receiver, or in both a transmitter and a receiver employed on one side of a bidirectional link The first and second settings can be associated with different swing voltages, edge rates, equalizations and/or impedances.

Abstract translation: 公开的实施例涉及改变发射机和/或接收机设置以处理由诸如功率状态或时钟启动事件的改变等预定事件引起的可靠性问题的系统。 一个实施例在正常操作模式期间操作发射机时使用第一设置，以及在预定事件之后的过渡期间操作发射机时的第二设置。 第二实施例在接收机中使用类似的第一和第二设置，或在双向链路的一侧采用的发射机和接收机两者中。第一和第二设置可以与不同的摆动电压，边缘速率，均衡和/或阻抗相关联 。

公开(公告)号：US12027197B2

公开(公告)日：2024-07-02

申请号：US17309770

申请日：2019-12-11

Applicant: Rambus Inc.

Inventor： Shahram Nikoukary ,  Jonghyun Cho ,  Anand Jai ,  Pradeep Batra ,  Lei Luo

IPC: G11C7/00 ,  G06F3/06 ,  G11C7/22 ,  G11C11/4076

CPC classification number: G11C11/4076 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/22 ,  G11C7/222

Abstract: A memory controller integrated circuit includes a clock signal generator circuit configured to generate a plurality of strobe signals. The memory controller integrated circuit further includes a memory interface circuit coupled to the clock signal generator circuit, the memory interface circuit configured to transmit the plurality of strobe signals to a memory module, wherein each of the plurality of strobe signals is offset with respect to an adjacent strobe signal, and transmit a plurality of data signals to the memory module, wherein a first subset of the plurality of data signals comprises a first nibble and is phase aligned with a first strobe signal of the plurality of strobe signals, and wherein a second subset of the plurality of data signals comprises a second nibble and is phase aligned with a second strobe signal of the plurality of strobe signals.

公开(公告)号：US20230326513A1

公开(公告)日：2023-10-12

申请号：US18103386

申请日：2023-01-30

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

IPC: G11C11/4076 ,  G11C11/4096 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G06F1/3237 ,  G06F1/04 ,  G06F1/3234 ,  G06F1/08 ,  G11C11/408

CPC classification number: G11C11/4076 ,  G11C11/4096 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  Y02D30/50 ,  G06F1/3237 ,  G06F1/04 ,  G06F1/3234 ,  G06F1/08 ,  G11C11/4087 ,  Y02D10/00 ,  G11C11/4074

Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

公开(公告)号：US11587605B2

公开(公告)日：2023-02-21

申请号：US17341048

申请日：2021-06-07

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

IPC: G06F1/04 ,  G06F1/08 ,  G06F1/3234 ,  G06F1/3237 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22

Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

公开(公告)号：US10249353B2

公开(公告)日：2019-04-02

申请号：US15604251

申请日：2017-05-24

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Lei Luo

IPC: G06F13/12 ,  G11C7/22 ,  G11C7/10 ,  G06F13/42 ,  G06F1/08 ,  G06F13/16 ,  G06F13/40

Abstract: In an illustrative embodiment, the memory circuit includes first and second data paths on which data is transferred for read and write memory operations and first and second mixer circuits for adjusting the phase of clock signals applied to their inputs. The mixer circuits are cross-coupled so that the outputs of the first and second mixers are both available to both the first and second data paths. One mixer is used to provide a first phase adjusted clock signal for use by the operating circuit and the other mixer is used to provide a second phase adjusted clock signal for use by a following operation whatever that may be.

公开(公告)号：US10026466B2

公开(公告)日：2018-07-17

申请号：US15616209

申请日：2017-06-07

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

IPC: G11C11/4076 ,  G11C11/4096 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G06F1/32 ,  G06F1/04 ,  G06F1/08 ,  G11C11/408

Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

公开(公告)号：US20180137902A1

公开(公告)日：2018-05-17

申请号：US15794177

申请日：2017-10-26

Applicant: Rambus Inc.

Inventor： Thomas Giovannini ,  Scott Best ,  Lei Luo ,  Ian Shaeffer

IPC: G11C7/22 ,  G11C29/56 ,  G11C29/50 ,  G11C29/02

CPC classification number: G11C7/222 ,  G11C7/227 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C29/56

Abstract: A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

公开(公告)号：US09691454B2

公开(公告)日：2017-06-27

申请号：US15160538

申请日：2016-05-20

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Lei Luo

IPC: G06F13/12 ,  G11C7/22 ,  G11C7/10 ,  G06F13/42 ,  G06F1/08 ,  G06F13/16 ,  G06F13/40

CPC classification number: G11C7/22 ,  G06F1/08 ,  G06F13/16 ,  G06F13/4068 ,  G06F13/4243 ,  G11C7/1072

Abstract: In an illustrative embodiment, the memory circuit includes first and second data paths on which data is transferred for read and write memory operations and first and second mixer circuits for adjusting the phase of clock signals applied to their inputs. The mixer circuits are cross-coupled so that the outputs of the first and second mixers are both available to both the first and second data paths. One mixer is used to provide a first phase adjusted clock signal for use by the operating circuit and the other mixer is used to provide a second phase adjusted clock signal for use by a following operation whatever that may be.

公开(公告)号：US09564879B1

公开(公告)日：2017-02-07

申请号：US14855244

申请日：2015-09-15

Applicant: Rambus Inc.

Inventor： Lei Luo ,  Barry W. Daly ,  Kambiz Kaviani ,  John Cronan Eble, III ,  John Wilson

IPC: H04B3/00 ,  H04L25/00 ,  H03K3/013

CPC classification number: H03K3/013 ,  G11C5/147 ,  G11C29/021 ,  G11C29/022 ,  G11C29/028 ,  H04L25/0296 ,  H04L25/06 ,  H04L25/08

Abstract: A signal on a transmitter tracks noise on a ground node in a manner decoupled from a positive node of a power supply. The signal is transmitted from the transmitter to the receiver. A reference voltage is generated on the receiver to track noise on a ground node in the receiver. Consequently, the received signal and the reference voltage have substantially the same noise characteristics, which become common mode noise that can be cancelled out when these two signals are compared against each other. In a further embodiment, the reference voltage is compared against a predetermined calibration pattern. An error signal is generated based on a difference between the sampler output and the predetermined calibration pattern. The error signal is then used to adjust the reference voltage so that the DC level of the reference voltage is positioned substantially in the middle of the received signal.

Abstract translation: 发射机上的信号以与电源的正节点分离的方式跟踪接地节点上的噪声。 信号从发射机发射到接收机。 在接收机上产生参考电压以跟踪接收机中接地节点上的噪声。 因此，接收信号和参考电压具有基本相同的噪声特性，这些噪声特性成为当这两个信号彼此进行比较时可以消除的共模噪声。 在另一实施例中，将参考电压与预定校准图案进行比较。 基于采样器输出和预定校准图案之间的差异产生误差信号。 然后使用误差信号来调整参考电压，使得参考电压的直流电平基本上位于接收信号的中间。

公开(公告)号：US20160343418A1

公开(公告)日：2016-11-24

申请号：US15228644

申请日：2016-08-04

Applicant: Rambus Inc.

Inventor： Thomas Giovannini ,  Scott Best ,  Lei Luo ,  Ian Shaeffer

IPC: G11C7/22 ,  G11C29/50 ,  G11C29/56

CPC classification number: G11C7/222 ,  G11C7/227 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C29/56

Abstract: A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.