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    Methods and systems for soft-decision decoding
    41.
    发明授权
    Methods and systems for soft-decision decoding 有权

    公开(公告)号：US09985653B2

    公开(公告)日：2018-05-29

    申请号：US14683656

    申请日：2015-04-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yaron Shany ,  Jun Jin Kong

    IPC: H03M13/15 ,  G06F11/10 ,  H03M13/37 ,  H03M13/45

    CPC classification number: H03M13/152 ,  H03M13/1515 ,  H03M13/1525 ,  H03M13/153 ,  H03M13/3707 ,  H03M13/451

    Abstract: At least one example embodiment discloses a method of soft-decision Wu decoding a code. The code is one of a generalized Reed-Solomon type and an alternant type. The method includes obtaining a module of the code. The module is a sub-module of at least a first extension module and a second extension module. The first extension module is defined by a set of first type constraints and the second extension module is defined by a set of second type constraints. The first type constraints are applicable to a first interpolation algorithm and a second interpolation algorithm and the second type constraints are applicable to the first interpolation algorithm. The method further includes determining a basis for the first extension module and converting the basis for the first extension module to a basis for the module.

    MEMORY DEVICES AND METHODS FOR OPERATING THE SAME
    42.
    发明申请
    MEMORY DEVICES AND METHODS FOR OPERATING THE SAME 审中-公开

    公开(公告)号：US20170337967A1

    公开(公告)日：2017-11-23

    申请号：US15156956

    申请日：2016-05-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Amit BERMAN ,  Jun Jin Kong ,  Uri Beitler

    IPC: G11C11/56

    CPC classification number: G11C11/5628 ,  G06F11/1072 ,  G11C11/5642 ,  G11C16/08 ,  G11C2211/5648

    Abstract: A memory device includes a memory including memory cells, each of the memory cells being configured to store multiple bits of data. The memory device includes a controller configured to map the levels of the memory cells to bits such that a first half of the levels have a bit with a first binary value in a desired bit position and a second half of the levels have a bit with a second binary value in the desired bit position. The first half of the levels are a first group of consecutive levels, and the second half of the levels are a second group of consecutive levels. The controller is configured to generate a distribution for writing the data to the memory cells based on the mapping, and write the data to the memory cells based on the determined distribution.

    Method of operating memory controller and devices including memory controller
    44.
    发明授权
    Method of operating memory controller and devices including memory controller 有权
    操作内存控制器和包括内存控制器的设备的方法

    公开(公告)号：US09460782B2

    公开(公告)日：2016-10-04

    申请号：US14205496

    申请日：2014-03-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Chang Kyu Seol ,  Jun Jin Kong ,  Hong Rak Son

    IPC: G06F12/02 ,  G11C11/56 ,  G11C7/10 ,  G11C16/34

    CPC classification number: G11C11/5642 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/3418 ,  G11C2211/5632

    Abstract: A method of operating a memory controller includes receiving a first data sequence and generating a coset representative sequence that can be divided into m-bit strings, where “m” is a natural number of at least 2; performing a first XOR operation on each of the m-bit strings in the coset representative sequence and binary bits; calculating all possible branch metrics according to a result of the first XOR operation; determining a survivor path sequence based on the all possible branch metrics; and performing a second XOR operation on the coset representative sequence and the survivor path sequence and generating an output sequence.

    Abstract translation: 一种操作存储器控制器的方法包括：接收第一数据序列并产生可被划分成m位串的陪集代表序列，其中“m”是至少为2的自然数; 在陪集代表序列和二进制位中的每个m位串上执行第一异或运算; 根据第一异或运算的结果计算所有可能的分支度量; 基于所有可能的分支度量来确定幸存者路径序列; 以及对陪集代表序列和幸存者路径序列执行第二异或运算并产生输出序列。

    Non-volatile memory device, operating method thereof, and storage device having the same
    46.
    发明授权
    Non-volatile memory device, operating method thereof, and storage device having the same 有权

    公开(公告)号：US11295818B2

    公开(公告)日：2022-04-05

    申请号：US17029265

    申请日：2020-09-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dong Jin Shin ,  Ji Su Kim ,  Dae Seok Byeon ,  Ji Sang Lee ,  Jun Jin Kong ,  Eun Chu Oh

    IPC: G11C7/00 ,  G11C16/26 ,  G11C16/10 ,  G11C5/14 ,  G11C16/08 ,  G11C16/32 ,  G11C11/56 ,  G11C16/24

    Abstract: A storage device including, a plurality of non-volatile memories configured to include a memory cell region including at least one first metal pad; and a peripheral circuit region including at least one second metal pad and vertically connected to the memory cell region by the at least one first metal pad and the at least one second metal pad, and a controller connected to the plurality of non-volatile memories through a plurality of channels and configured to control the plurality of non-volatile memories, wherein the controller selects one of a first read operation mode and a second read operation mode and transfers a read command corresponding to the selected read operation mode to the plurality of non-volatile memories, wherein one sensing operation is performed to identify one program state among program sates in the first read operation mode, and wherein at least two sensing operations are performed to identify the one program state among the program states in the second read operation mode.

    Semiconductor memory device, controller, and memory system
    48.
    发明授权
    Semiconductor memory device, controller, and memory system 有权

    公开(公告)号：US10824507B2

    公开(公告)日：2020-11-03

    申请号：US16372047

    申请日：2019-04-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myung Kyu Lee ,  Jun Jin Kong ,  Ki Jun Lee ,  Sung Hye Cho ,  Dae Hyun Kim ,  Yong Gyu Chu

    IPC: G06F11/10 ,  H03M13/29 ,  G11C29/52

    Abstract: Disclosed are a semiconductor memory device, a controller, and a memory system. The semiconductor memory device includes a memory cell array including a plurality of memory cells, and an error correcting code (ECC) decoder configured to receive first data and a parity output from selected memory cells of the memory cell array. The ECC decoder generates a syndrome based on the first data and the parity, generates a decoding status flag (DSF) indicating a type of an error of the first data by the syndrome, and outputs the second data and the DSF to an external device outside of the semiconductor memory device when a read operation of the semiconductor memory device is performed.

    Bose-chaudhuri-hocquenchem (BCH) encoding and decoding tailored for redundant array of inexpensive disks (RAID)
    50.
    发明授权
    Bose-chaudhuri-hocquenchem (BCH) encoding and decoding tailored for redundant array of inexpensive disks (RAID) 有权

    公开(公告)号：US10387254B2

    公开(公告)日：2019-08-20

    申请号：US15730943

    申请日：2017-10-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Moshe Twitto ,  Yaron Shany ,  Avner Dor ,  Elona Erez ,  Jun Jin Kong

    IPC: G06F11/10 ,  G06F3/06 ,  H03M13/15 ,  H03M13/29

    Abstract: A method of encoding generalized concatenated error-correcting codes includes providing a parity matrix {tilde over (H)}j of a j-th layer code and predefined syndrome {tilde over (s)} of length n−{tilde over (k)}j, where the first n-kl coordinates are zero, n is a length of a codeword c of a first layer BCH code Cl of dimension {tilde over (k)}j, codeword c satisfies {tilde over (H)}jc={tilde over (s)}, a first layer code includes only a BCH code, and each subsequent layer includes a Reed-Solomon (RS) stage followed by a BCH code; finding a square matrix R, of dimension (n−{tilde over (k)}j)(n−{tilde over (k)}j) such that Rj{tilde over (H)}j=(A|I), where A is an arbitrary matrix, Rj=(Qj|Tj), where Q has n−kl columns Tj and has k1−{tilde over (k)}j columns; finding a vector c−(a b) where a is a vector of length {tilde over (k)}j and b is a vector of length n−{tilde over (k)}j; and solving ( A | I ) ⁢ ( a b ) = ( Q j | T j ) ⁢ s ~ = T j ⁢ s ⁢ ⁢ where ⁢ ⁢ a = 0 ⁢ ⁢ and ⁢ ⁢ b = T j ⁢ s , where a=0 and b=Tjs, and codeword c is nonzero only on the last n−{tilde over (k)}j=n−kj bits.

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