公开(公告)号：US20150294693A1

公开(公告)日：2015-10-15

申请号：US14681570

申请日：2015-04-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya ONUKI ,  Kiyoshi KATO ,  Yutaka SHIONOIRI ,  Tomoaki ATSUMI ,  Takanori MATSUZAKI ,  Hiroki INOUE ,  Shuhei NAGATSUKA ,  Yuto YAKUBO

IPC: G11C5/02 ,  H01L27/12 ,  G11C5/06 ,  H01L29/24

CPC classification number: G11C5/025 ,  G11C11/4091 ,  G11C11/4097 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/24

Abstract: Provided is a semiconductor device which can achieve a reduction in its area, reduction in power consumption, and operation at a high speed. A semiconductor device 10 has a structure in which a circuit 31 including a memory circuit and a circuit 32 including an amplifier circuit are stacked. With this structure, the memory circuit and the amplifier circuit can be mounted on the semiconductor device 10 while the increase in the area of the semiconductor device 10 is suppressed. Thus, the area of the semiconductor device 10 can be reduced. Further, the circuits are formed using OS transistors, so that the memory circuit and the amplifier circuit which have low off-state current and which can operate at a high speed can be formed. Therefore, a reduction in power consumption and improvement in operation speed of the semiconductor device 10 can be achieved.

Abstract translation: 提供一种能够实现面积减小，功耗降低，高速运转的半导体装置。 半导体器件10具有堆叠包括存储电路的电路31和包括放大电路的电路32的结构。 利用这种结构，可以在半导体器件10的面积的增加被抑制的同时将存储电路和放大器电路安装在半导体器件10上。 因此，可以减小半导体器件10的面积。 此外，使用OS晶体管形成电路，从而可以形成具有低截止电流并且可以高速操作的存储电路和放大器电路。 因此，可以实现半导体器件10的功耗的降低和操作速度的提高。

公开(公告)号：US20140191719A1

公开(公告)日：2014-07-10

申请号：US14208844

申请日：2014-03-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei NAGATSUKA ,  Akihiro KIMURA

IPC: H02J7/02

CPC classification number: H02J50/40 ,  H01M10/44 ,  H02J7/0052 ,  H02J7/025 ,  H02J17/00 ,  H02J50/10 ,  H02J50/27 ,  H04B1/3883 ,  Y10T307/696

Abstract: An electric power charge and discharge system for an electronic device having a battery, by which the electronic device can be used for a long period of time. In a wireless communication device including a wireless driving portion including a first battery and a wireless charging portion including a second battery, the first battery is charged by electric power from a fixed power supply and the second battery is charged by using electromagnetic waves existing in an external space. Further, the first battery and the second battery are discharged alternately, and during a period in which the first battery is discharged, the second battery is charged.

Abstract translation: 一种用于具有电池的电子设备的电力充放电系统，通过该电池，电子设备可以长时间使用。 在包括第一电池的无线驱动部和包括第二电池的无线充电部的无线通信装置中，通过来自固定电源的电力对第一电池进行充电，并且通过使用存在于第二电池的电磁波对第二电池进行充电 外部空间。 此外，第一电池和第二电池交替放电，并且在第一电池放电的时段期间，第二电池被充电。

公开(公告)号：US20230307012A1

公开(公告)日：2023-09-28

申请号：US18203717

申请日：2023-05-31

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tatsuya ONUKI ,  Shuhei NAGATSUKA

IPC: G11C5/06 ,  G11C11/4074 ,  G11C11/4091 ,  H01L29/786 ,  G11C7/10 ,  H10B12/00

CPC classification number: G11C5/063 ,  G11C11/4074 ,  G11C11/4091 ,  H01L29/7869 ,  G11C7/1051 ,  H10B12/30 ,  H10B12/50

Abstract: A memory device that operates at high speed is provided.
The memory device includes first and second memory cells, first and second bit lines, first and second switches, and a sense amplifier. The sense amplifier comprises a first node and a second node. The first memory cell is electrically connected to the first node through the first bit line and the first switch, and the second memory cell is electrically connected to the second node through the second bit line and the second switch. The sense amplifier amplifies the potential difference between the first node and the second node. The first memory cell and the second memory cell include an oxide semiconductor in a channel formation region.

公开(公告)号：US20230040508A1

公开(公告)日：2023-02-09

申请号：US17788050

申请日：2020-12-14

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tatsuya ONUKI ,  Munehiro KOZUMA ,  Takeshi AOKI ,  Takanori MATSUZAKI ,  Yuki OKAMOTO ,  Masashi OOTA ,  Shuhei NAGATSUKA ,  Hitoshi KUNITAKE ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  G06N3/02 ,  H01L29/423 ,  H01L27/105

Abstract: To provide a semiconductor device with a novel structure. The semiconductor device includes an accelerator. The accelerator includes a first memory circuit, a second memory circuit, and an arithmetic circuit. The first memory circuit includes a first transistor. The second memory circuit includes a second transistor. Each of the first transistor and the second transistor includes a semiconductor layer including a metal oxide in a channel formation region. The arithmetic circuit includes a third transistor. The third transistor includes a semiconductor layer including silicon in a channel formation region. The first transistor and the second transistor are provided in different layers. The layer including the first transistor is provided over a layer including the third transistor. The layer including the second transistor is provided over the layer including the first transistor. The data retention characteristics of the first memory circuit are different from those of the second memory circuit.

公开(公告)号：US20220020881A1

公开(公告)日：2022-01-20

申请号：US17296358

申请日：2019-11-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kentaro SUGAYA ,  Ryota HODO ,  Kenichiro MAKINO ,  Shuhei NAGATSUKA

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/308 ,  H01L27/12

Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a plurality of transistors; each of the plurality of transistors includes a first insulator, a first oxide, a second oxide, a first conductor, a second conductor, a third oxide, a second insulator, and a third conductor; the third oxide included in one of the plurality of transistors and the third oxide included in another of the plurality of transistors, which is adjacent to the one of the plurality of transistors, are provided to be apart from each other in the channel width direction of the plurality of transistors; the second insulator included in one of the plurality of transistors includes a region continuous with the second insulator included in another of the plurality of transistors, which is adjacent to the one of the plurality of transistors; and the third conductor included in one of the plurality of transistors includes a region continuous with the third conductor included in another of the plurality of transistors, which is adjacent to the one of the plurality of transistors.

公开(公告)号：US20210367078A1

公开(公告)日：2021-11-25

申请号：US16975309

申请日：2019-02-21

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Hitoshi KUNITAKE ,  Yoko TSUKAMOTO

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/66

Abstract: A semiconductor device in which an electrification phenomenon that leads to characteristic fluctuations, element deterioration, abnormality in shape, or dielectric breakdown is inhibited is provided.
The semiconductor device includes a first region and a second region over the same plane. The first region includes a transistor. The second region includes a dummy transistor. The transistor includes a first wiring layer, a semiconductor layer including an oxide and provided above the first wiring layer, a second wiring layer provided above the semiconductor layer, and a third wiring layer provided above the second wiring layer. The dummy transistor has the same area as one or more selected from the first wiring layer, the second wiring layer, the semiconductor layer, and the third wiring layer.

公开(公告)号：US20210158846A1

公开(公告)日：2021-05-27

申请号：US16625826

申请日：2018-06-19

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tatsuya ONUKI ,  Shuhei NAGATSUKA

IPC: G11C5/06 ,  G11C11/4091 ,  G11C11/4074 ,  H01L29/786 ,  H01L27/108

Abstract: A memory device that operates at high speed is provided.
The memory device includes first and second memory cells, first and second bit lines, first and second switches, and a sense amplifier. The sense amplifier comprises a first node and a second node. The first memory cell is electrically connected to the first node through the first bit line and the first switch, and the second memory cell is electrically connected to the second node through the second bit line and the second switch. The sense amplifier amplifies the potential difference between the first node and the second node. The first memory cell and the second memory cell include an oxide semiconductor in a channel formation region.

公开(公告)号：US20180090976A1

公开(公告)日：2018-03-29

申请号：US15822483

申请日：2017-11-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei NAGATSUKA ,  Akihiro KIMURA

IPC: H02J7/02 ,  H01M10/44 ,  H02J50/10 ,  H04B1/3883 ,  H02J7/00

CPC classification number: H02J50/40 ,  H01M10/44 ,  H02J7/0052 ,  H02J7/025 ,  H02J17/00 ,  H02J50/10 ,  H02J50/27 ,  H04B1/3883 ,  Y10T307/696

Abstract: An electric power charge and discharge system for an electronic device having a battery, by which the electronic device can be used for a long period of time. In a wireless communication device including a wireless driving portion including a first battery and a wireless charging portion including a second battery, the first battery is charged by electric power from a fixed power supply and the second battery is charged by using electromagnetic waves existing in an external space. Further, the first battery and the second battery are discharged alternately, and during a period in which the first battery is discharged, the second battery is charged.

公开(公告)号：US20180075900A1

公开(公告)日：2018-03-15

申请号：US15695128

申请日：2017-09-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko ISHIZU ,  Shuhei NAGATSUKA

IPC: G11C11/419 ,  G11C7/22 ,  G11C16/04 ,  G11C16/24 ,  G11C16/28 ,  G11C7/06 ,  G11C7/14 ,  H01L27/11529

CPC classification number: G11C11/419 ,  G11C7/065 ,  G11C7/14 ,  G11C7/227 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/4099 ,  G11C16/0425 ,  G11C16/24 ,  G11C16/28 ,  H01L27/11529 ,  H01L27/1156 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A memory device includes a memory cell, a replica cell, a read circuit, a write wordline, a read wordline, a dummy read wordline, a write bitline, a read bitline, a reference bitline, a sourceline, and a first wiring. The memory cell is electrically connected to the write wordline, the read wordline, the write bitline, the read bitline, and the sourceline. The read circuit outputs a potential based on the result of comparing the potential of the reference bitline and the potential of the read bitline. The replica cell includes a first transistor and a second transistor. The first transistor and the second transistor are electrically connected to each other in series between the bitline and the sourceline. A gate of the first transistor and a gate of the second transistor are electrically connected to a dummy read wordline and the first wiring, respectively.

公开(公告)号：US20170263774A1

公开(公告)日：2017-09-14

申请号：US15604934

申请日：2017-05-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daisuke MATSUBAYASHI ,  Yoshiyuki KOBAYASHI ,  Shuhei NAGATSUKA ,  Yutaka SHIONOIRI

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/78648 ,  H01L29/78696

Abstract: A transistor having favorable electrical characteristics. A transistor suitable for miniaturization. A transistor having a high switching speed. One embodiment of the present invention is a semiconductor device that includes a transistor. The transistor includes an oxide semiconductor, a gate electrode, and a gate insulator. The oxide semiconductor includes a first region in which the oxide semiconductor and the gate electrode overlap with each other with the gate insulator positioned therebetween. The transistor has a threshold voltage higher than 0 V and a switching speed lower than 100 nanoseconds.