公开(公告)号：US20080128863A1

公开(公告)日：2008-06-05

申请号：US11969154

申请日：2008-01-03

申请人： Yasuichi KONDO ,  Wataru Hirasawa ,  Nobuyuki Sugii

发明人： Yasuichi KONDO ,  Wataru Hirasawa ,  Nobuyuki Sugii

IPC分类号： H01L25/00

CPC分类号： C23C16/45506 ,  C23C16/22 ,  C23C16/45523 ,  C23C16/45563 ,  C23C16/45578 ,  C23C16/4584 ,  C23C16/46 ,  C30B25/00 ,  C30B25/02 ,  C30B29/403 ,  C30B29/52 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/2807 ,  H01L29/1054 ,  H01L29/66575 ,  H01L29/78

摘要： Gases for film formation are introduced from a plurality of holes provided at a gas nozzle into a processing chamber of a batch-type CVD film-forming apparatus to cause a turbulence of the gases within the processing chamber. In the state where the chamber is kept at a pressure within an atmospheric and quasi-atmospheric pressure region, a silicon-germanium film is epitaxially grown on a semiconductor wafer placed within the processing chamber. Subsequently, a strained silicon film is epitaxially grown on the silicon-germanium film. Thereafter, a semiconductor element is formed in the semiconductor wafer on which the silicon-germanium film and the strained silicon film have been formed, respectively.

摘要翻译： 用于成膜的气体从设置在气体喷嘴的多个孔引入到间歇式CVD成膜装置的处理室中，以引起处理室内的气体的紊流。 在室保持在大气压和准大气压区域内的压力的状态下，在放置在处理室内的半导体晶片上外延生长硅 - 锗膜。 随后，在硅 - 锗膜上外延生长应变硅膜。 此后，分别在其上形成有硅 - 锗膜和应变硅膜的半导体晶片中形成半导体元件。

公开(公告)号：US07045412B2

公开(公告)日：2006-05-16

申请号：US10898257

申请日：2004-07-26

申请人： Nobuyuki Sugii ,  Masatoshi Morikawa ,  Isao Yoshida ,  Katsuyoshi Washio

发明人： Nobuyuki Sugii ,  Masatoshi Morikawa ,  Isao Yoshida ,  Katsuyoshi Washio

IPC分类号： H01L21/8238

CPC分类号： H01L29/66659 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/165 ,  H01L29/7835 ,  H03F3/601 ,  Y10S438/933

摘要： In a semiconductor multi-layer structure in which a first SiGe layer having a first conductivity-type and high impurity concentration, a second SiGe layer having the first conductivity-type and a low impurity concentration and a Si layer having a low impurity concentration are formed one on another in this order on a Si substrate of the first conductivity-type, a channel is formed in a part of the Si layer and a source electrode passes through the second SiGe layer of low impurity concentration to electrically contact the first SiGe layer of high impurity concentration or the substrate.

公开(公告)号：US06936875B2

公开(公告)日：2005-08-30

申请号：US10673789

申请日：2003-09-30

申请人： Nobuyuki Sugii ,  Kazuhiro Ohnishi ,  Katsuyoshi Washio

发明人： Nobuyuki Sugii ,  Kazuhiro Ohnishi ,  Katsuyoshi Washio

IPC分类号： H01L21/764 ,  H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/10 ,  H01L29/786 ,  H01L29/80

CPC分类号： H01L29/785 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/78648 ,  H01L29/78687 ,  H01L29/802

摘要： With the invention, it is possible to avoid deterioration in short-channel characteristics, caused by a silicon germanium layer coming into contact with the channel of a strained SOI transistor. Further, it is possible to fabricate a double-gate type of strained SOI transistor or to implement mixedly mounting the strained SOI transistor and a conventional silicon or SOI transistor on the same wafer. According to the invention, for example, a strained silicon layer is grown on a strain-relaxed silicon germanium layer, and subsequently, portions of the silicon germanium layer are removed, thereby constituting a channel layer in the strained silicon layer.

摘要翻译： 利用本发明，可以避免由与应变SOI晶体管的沟道接触的硅锗层引起的短沟道特性的劣化。 此外，可以制造双栅型应变SOI晶体管，或者在同一晶片上实现将应变SOI晶体管和常规硅或SOI晶体管混合安装。 根据本发明，例如，在应变松弛硅锗层上生长应变硅层，随后去除硅锗层的部分，从而在应变硅层中构成沟道层。

公开(公告)号：US06888162B2

公开(公告)日：2005-05-03

申请号：US10354121

申请日：2003-01-30

申请人： Shinya Yamaguchi ,  Masanobu Miyao ,  Kiyokazu Nakagawa ,  Nobuyuki Sugii

发明人： Shinya Yamaguchi ,  Masanobu Miyao ,  Kiyokazu Nakagawa ,  Nobuyuki Sugii

IPC分类号： G06F15/78 ,  G02F1/136 ,  G02F1/1368 ,  H01L21/20 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/786

CPC分类号： H01L21/02686 ,  H01L21/2026 ,  H01L27/1281 ,  H01L27/1285 ,  H01L27/1296 ,  H01L29/04 ,  H01L29/66742 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/78654 ,  H01L29/78675 ,  H01L29/78684

摘要： An electronic apparatus employs a polycrystalline semiconductor thin film structure formed of an insulating substrate and a plurality of polycrystalline layers laminated on the insulating substrate. A plurality of transistors are formed at the surface of the polycrystalline semiconductor thin film structure, each transistor being formed in a region of one of a plurality of crystal grains disseminated on the surface of the polycrystalline layers. A number of crystal grains in each of the polycrystalline layers is gradually reduced from a lower layer to an upper layer.

摘要翻译： 电子设备采用由绝缘基板和层叠在绝缘基板上的多个多晶层形成的多晶半导体薄膜结构。 在多晶半导体薄膜结构的表面形成多个晶体管，每个晶体管形成在多晶层的表面上散布的多个晶粒中的一个晶体管的区域中。 各个多晶层中的多个晶粒从下层逐渐减小到上层。

公开(公告)号：US20050003573A1

公开(公告)日：2005-01-06

申请号：US10898257

申请日：2004-07-26

申请人： Nobuyuki Sugii ,  Masatoshi Morikawa ,  Isao Yoshida ,  Katsuyoshi Washio

发明人： Nobuyuki Sugii ,  Masatoshi Morikawa ,  Isao Yoshida ,  Katsuyoshi Washio

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/10 ,  H01L29/165 ,  H01L29/78 ,  H03F3/60 ,  H01L29/06

CPC分类号： H01L29/66659 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/165 ,  H01L29/7835 ,  H03F3/601 ,  Y10S438/933

摘要： In a semiconductor multi-layer structure in which a first SiGe layer having a first conductivity-type and high impurity concentration, a second SiGe layer having the first conductivity-type and a low impurity concentration and a Si layer having a low impurity concentration are formed one on another in this order on a Si substrate of the first conductivity-type, a channel is formed in a part of the Si layer and a source electrode passes through the second SiGe layer of low impurity concentration to electrically contact the first SiGe layer of high impurity concentration or the substrate.

摘要翻译： 在具有第一导电型和高杂质浓度的第一SiGe层的半导体多层结构中，形成具有第一导电型和低杂质浓度的第二SiGe层和具有低杂质浓度的Si层 在第一导电类型的Si衬底上依次另一个，在Si层的一部分中形成沟道，并且源极通过低杂质浓度的第二SiGe层，以电接触第一SiGe层的第一SiGe层 高杂质浓度或底物。

公开(公告)号：US5468806A

公开(公告)日：1995-11-21

申请号：US347847

申请日：1994-12-01

申请人： Kiyoshi Yamamoto ,  Nobuyuki Sugii ,  Koichi Kubo ,  Michiharu Ichikawa ,  Hisao Yamauchi

发明人： Kiyoshi Yamamoto ,  Nobuyuki Sugii ,  Koichi Kubo ,  Michiharu Ichikawa ,  Hisao Yamauchi

IPC分类号： H01L39/24 ,  C30B25/16

CPC分类号： H01L39/2461 ,  Y10S505/729 ,  Y10S505/73

摘要： Disclosed is a method of manufacturing a thin film of an oxide superconductor represented by formula Sr.sub.1-x Nd.sub.x CuO.sub.2 on a substrate. The oxide superconductor has a tetragonal crystal structure, the lattice constant in a-axis falling within a range of between 0.385 nm and 0.410 nm, and the lattice constant in c-axis being an integer number of times as much as a level falling within a range of between 0.310 nm and 0.350 nm. The method includes the steps of forming by epitaxial growth a film of a crystal having lattice constants close to those of the crystal of said oxide superconductor on a substrate, and forming a thin film of the oxide superconductor of a tetragonal crystal structure represented by general formula (I) by a thin film-forming technique.

摘要翻译： 公开了在基板上制造由式Sr1-xNdxCuO2表示的氧化物超导体的薄膜的方法。 氧化物超导体具有四方晶体结构，a轴的晶格常数落在0.385nm〜0.410nm的范围内，c轴的晶格常数为落入 范围在0.310nm和0.350nm之间。 该方法包括以下步骤：通过在衬底上外延生长具有接近所述氧化物超导体的晶体的晶格常数的晶体的膜，并形成由通式（I）表示的四方晶体结构的氧化物超导体的薄膜 （I）通过薄膜形成技术。

公开(公告)号：US20110188329A1

公开(公告)日：2011-08-04

申请号：US13086377

申请日：2011-04-13

申请人： Takayuki Kawahara ,  Masanao Yamaoka ,  Nobuyuki Sugii

发明人： Takayuki Kawahara ,  Masanao Yamaoka ,  Nobuyuki Sugii

IPC分类号： G11C7/00 ,  H01L27/088

CPC分类号： H01L21/84 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/1203 ,  H01L27/153

摘要： The semiconductor integrated circuit (1) has a memory (4) and a logic circuit (5), which are mixedly palletized on a silicon substrate (2). The memory includes a partially-depleted type nMOS (6) having an SOI structure and formed on UTB (3). The partially-depleted type nMOS has a backgate region (14) under UTB, to which a voltage can be applied independently of a corresponding gate terminal. The logic circuit includes an nMOS (7) and a pMOS (8), and both are of a fully-depleted type, formed on UTB and have an SOI structure. The fully-depleted type nMOS and pMOS have backgate regions (14, 22) under respective UTBs, to which voltages can be applied independently of the corresponding gate terminals

摘要翻译： 半导体集成电路（1）具有在硅衬底（2）上混合堆垛的存储器（4）和逻辑电路（5）。 存储器包括具有SOI结构并形成在UTB（3）上的部分耗尽型nMOS（6）。 部分耗尽型nMOS在UTB之下具有背栅区域（14），独立于对应的栅极端子可以施加电压。 逻辑电路包括nMOS（7）和pMOS（8），并且它们都是完全耗尽型的，形成在UTB上并具有SOI结构。 完全耗尽型nMOS和pMOS在相应的UTB下具有背栅区域（14,22），可以独立于对应的栅极端子施加电压

公开(公告)号：US20050173705A1

公开(公告)日：2005-08-11

申请号：US11103465

申请日：2005-04-12

申请人： Yasuichi Kondo ,  Wataru Hirasawa ,  Nobuyuki Sugii

发明人： Yasuichi Kondo ,  Wataru Hirasawa ,  Nobuyuki Sugii

IPC分类号： C23C16/42 ,  C23C16/44 ,  C23C16/455 ,  C30B25/00 ,  H01L21/20 ,  H01L21/205 ,  H01L29/78 ,  H01L29/04 ,  C30B1/00 ,  H01L31/062

CPC分类号： C23C16/45506 ,  C23C16/22 ,  C23C16/45523 ,  C23C16/45563 ,  C23C16/45578 ,  C23C16/4584 ,  C23C16/46 ,  C30B25/00 ,  C30B25/02 ,  C30B29/403 ,  C30B29/52 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/2807 ,  H01L29/1054 ,  H01L29/66575 ,  H01L29/78

摘要： Gases for film formation are introduced from a plurality of holes provided at a gas nozzle into a processing chamber of a batch-type CVD film-forming apparatus to cause a turbulence of the gases within the processing chamber. In the state where the chamber is kept at a pressure within an atmospheric and quasi-atmospheric pressure region, a silicon-germanium film is epitaxially grown on a semiconductor wafer placed within the processing chamber. Subsequently, a strained silicon film is epitaxially grown on the silicon-germanium film. Thereafter, a semiconductor element is formed in the semiconductor wafer on which the silicon-germanium film and the strained silicon film have been formed, respectively.

摘要翻译： 用于成膜的气体从设置在气体喷嘴的多个孔引入到间歇式CVD成膜装置的处理室中，以引起处理室内的气体的紊流。 在室保持在大气压和准大气压区域内的压力的状态下，在放置在处理室内的半导体晶片上外延生长硅 - 锗膜。 随后，在硅 - 锗膜上外延生长应变硅膜。 此后，分别在其上形成有硅 - 锗膜和应变硅膜的半导体晶片中形成半导体元件。

公开(公告)号：US06545294B1

公开(公告)日：2003-04-08

申请号：US09571937

申请日：2000-05-16

申请人： Shinya Yamaguchi ,  Masanobu Miyao ,  Kiyokazu Nakagawa ,  Nobuyuki Sugii

发明人： Shinya Yamaguchi ,  Masanobu Miyao ,  Kiyokazu Nakagawa ,  Nobuyuki Sugii

IPC分类号： H01L2904

CPC分类号： H01L21/02686 ,  H01L21/2026 ,  H01L27/1281 ,  H01L27/1285 ,  H01L27/1296 ,  H01L29/04 ,  H01L29/66742 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/78654 ,  H01L29/78675 ,  H01L29/78684

摘要： The present invention provides an apparatus having a semiconductor device including a plurality of transistors formed on respective single crystal silicon regions of enlarged grain size. On a polycrystalline silicon layer, projections at regular intervals are formed by using anisotropic etching and a photomask. The tips of projections are composed of single crystal silicon of a specific crystal orientation selectively left by the anisotropic etching, which is a candidate for nuclei of amorphous silicon to be deposited thereon. By iterating the above process a plurality of times, and by gradually enlarging the pitch, span, size and height of projections, the size of the crystal grains of silicon at the surface may be enlarged to the extent required. Thereby, silicon crystal grains of large grain size with the crystal orientation aligned may be formed at controllable positions.

摘要翻译： 本发明提供一种具有半导体器件的装置，该半导体器件包括形成在增大晶粒尺寸的各个单晶硅区域上的多个晶体管。 在多晶硅层上，通过使用各向异性蚀刻和光掩模形成规则间隔的突起。 突起的尖端由通过各向异性蚀刻选择性留下的特定晶体取向的单晶硅组成，其是沉积在其上的非晶硅的核的候选者。 通过多次迭代上述处理，并且通过逐渐扩大突起的间距，跨度，尺寸和高度，可以将表面处的硅晶粒的尺寸扩大到所需的程度。 由此，可以在可控位置形成具有晶体取向取向的大晶粒尺寸的硅晶粒。

公开(公告)号：US08878244B2

公开(公告)日：2014-11-04

申请号：US11969154

申请日：2008-01-03

申请人： Yasuichi Kondo ,  Wataru Hirasawa ,  Nobuyuki Sugii

发明人： Yasuichi Kondo ,  Wataru Hirasawa ,  Nobuyuki Sugii

IPC分类号： H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  C23C16/455 ,  H01L29/10 ,  C23C16/22 ,  C23C16/458 ,  C23C16/46 ,  C30B25/00 ,  C30B25/02 ,  C30B29/40 ,  C30B29/52 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

CPC分类号： C23C16/45506 ,  C23C16/22 ,  C23C16/45523 ,  C23C16/45563 ,  C23C16/45578 ,  C23C16/4584 ,  C23C16/46 ,  C30B25/00 ,  C30B25/02 ,  C30B29/403 ,  C30B29/52 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/2807 ,  H01L29/1054 ,  H01L29/66575 ,  H01L29/78

摘要： Gases for film formation are introduced from a plurality of holes provided at a gas nozzle into a processing chamber of a batch-type CVD film-forming apparatus to cause a turbulence of the gases within the processing chamber. In the state where the chamber is kept at a pressure within an atmospheric and quasi-atmospheric pressure region, a silicon-germanium film is epitaxially grown on a semiconductor wafer placed within the processing chamber. Subsequently, a strained silicon film is epitaxially grown on the silicon-germanium film. Thereafter, a semiconductor element is formed in the semiconductor wafer on which the silicon-germanium film and the strained silicon film have been formed, respectively.

摘要翻译： 用于成膜的气体从设置在气体喷嘴的多个孔引入到间歇式CVD成膜装置的处理室中，以引起处理室内的气体的紊流。 在室保持在大气压和准大气压区域内的压力的状态下，在放置在处理室内的半导体晶片上外延生长硅 - 锗膜。 随后，在硅 - 锗膜上外延生长应变硅膜。 此后，分别在其上形成有硅 - 锗膜和应变硅膜的半导体晶片中形成半导体元件。