公开(公告)号：US09831707B2

公开(公告)日：2017-11-28

申请号：US14208844

申请日：2014-03-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei Nagatsuka ,  Akihiro Kimura

IPC: H02J7/00 ,  H02J7/02 ,  H02J50/10 ,  H01M10/44 ,  H02J17/00 ,  H04B1/3883

CPC classification number: H02J50/40 ,  H01M10/44 ,  H02J7/0052 ,  H02J7/025 ,  H02J17/00 ,  H02J50/10 ,  H02J50/27 ,  H04B1/3883 ,  Y10T307/696

Abstract: An electric power charge and discharge system for an electronic device having a battery, by which the electronic device can be used for a long period of time. In a wireless communication device including a wireless driving portion including a first battery and a wireless charging portion including a second battery, the first battery is charged by electric power from a fixed power supply and the second battery is charged by using electromagnetic waves existing in an external space. Further, the first battery and the second battery are discharged alternately, and during a period in which the first battery is discharged, the second battery is charged.

公开(公告)号：US09793276B2

公开(公告)日：2017-10-17

申请号：US14935607

申请日：2015-11-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Shuhei Nagatsuka ,  Hiroki Inoue ,  Takanori Matsuzaki

IPC: H01L27/105 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/12

CPC classification number: H01L27/108 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/1156 ,  H01L27/1225

Abstract: A semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limitation on the number of times of writing. In the semiconductor device, a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is provided in matrix and a wiring (also called a bit line) for connecting one memory cell to another memory cell and a source or drain electrode of the first transistor are electrically connected to each other through a source or drain electrode of the second transistor. Accordingly, the number of wirings can be smaller than that in the case where the source or drain electrode of the first transistor and the source or drain electrode of the second transistor are connected to different wirings. Thus, the degree of integration of the semiconductor device can be increased.

公开(公告)号：US09748274B2

公开(公告)日：2017-08-29

申请号：US15160076

申请日：2016-05-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko Ishizu ,  Shuhei Nagatsuka ,  Tatsuya Onuki ,  Yutaka Shionoiri ,  Naoaki Tsutsui ,  Shunpei Yamazaki

IPC: G11C11/401 ,  H01L27/12 ,  G11C5/06 ,  G11C11/4097 ,  G11C29/04 ,  H01L27/108 ,  H01L27/1156

CPC classification number: H01L27/1207 ,  G11C5/063 ,  G11C11/401 ,  G11C11/4097 ,  G11C2029/0403 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/1255

Abstract: A memory device in which the number of films is reduced. The memory device includes a circuit and a wiring. The circuit includes a first memory cell and a second memory cell. The first memory cell includes a first transistor, a second transistor, and a first capacitor. The second memory cell includes a third transistor, a fourth transistor, and a second capacitor. The second memory cell is stacked over the first memory cell. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and the first capacitor. One of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor and the second capacitor. A gate of the first transistor and a gate of the third transistor are electrically connected to the wiring.

公开(公告)号：US09747962B2

公开(公告)日：2017-08-29

申请号：US15125658

申请日：2015-03-05

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shuhei Nagatsuka ,  Tomoaki Atsumi ,  Shunpei Yamazaki

IPC: G11C7/22 ,  G11C11/405 ,  H01L29/786 ,  G11C11/56 ,  G11C27/00 ,  H01L27/06 ,  H01L27/12 ,  G11C5/14 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/088

CPC classification number: G11C7/22 ,  G11C5/14 ,  G11C11/405 ,  G11C11/565 ,  G11C27/005 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/786

Abstract: A semiconductor device which can write and read multilevel data is provided. A node connecting a source or a drain of an OS transistor and a gate of an OS transistor can hold the distribution of a plurality of potentials. A circuit configuration is employed in which the potential of the node is changed by capacitive coupling to control a conduction state of the OS transistor whose gate is connected thereto so that the potential of a gate of a Si transistor is changed. The potential of the gate of the Si transistor is changed positively in accordance with the potential change by capacitive coupling and is changed negatively in accordance with another transistor. In accordance with a change in value of current flowing through the Si transistor is detected, written data is read.

公开(公告)号：US09716100B2

公开(公告)日：2017-07-25

申请号：US14643621

申请日：2015-03-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki Atsumi ,  Shuhei Nagatsuka

IPC: H01L27/108 ,  H01L27/1156 ,  H01L27/11551 ,  G11C7/10 ,  G11C7/16 ,  G11C11/405 ,  G11C11/408 ,  H01L27/12

CPC classification number: H01L27/1156 ,  G11C7/1006 ,  G11C7/16 ,  G11C11/405 ,  G11C11/4085 ,  H01L27/11551 ,  H01L27/1225

Abstract: A novel semiconductor device that can write and read multilevel data is provided. A memory cell includes a bit line, a power supply line, first and second nodes, first to fourth transistors, and first and second capacitors. One of two divided multilevel data is written to the first node through the first transistor. The other of the divided multilevel data is written to the second node through the second transistor. A gate of the third transistor is connected to the first node, and a gate of the fourth transistor is connected to the second node. The third and fourth transistors control electrical continuity between the bit line and the power supply line. Each of the first and second transistors preferably includes an oxide semiconductor in a semiconductor layer.

公开(公告)号：US09647665B2

公开(公告)日：2017-05-09

申请号：US14967553

申请日：2015-12-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroki Inoue ,  Takanori Matsuzaki ,  Shuhei Nagatsuka ,  Takahiko Ishizu ,  Tatsuya Onuki

IPC: H03L5/00 ,  H03K19/0185 ,  H03K19/00

CPC classification number: H03K19/018521 ,  H03K3/356104 ,  H03K19/0016

Abstract: To provide a semiconductor device that inhibits unexpected output of a high-level signal immediately after the rise of a power supply voltage. A semiconductor device includes a first buffer circuit, a level shifter circuit, and a second buffer circuit. A first potential is supplied to the first buffer circuit, and a second potential is supplied to the level shifter circuit and the second buffer circuit; consequently, the semiconductor device returns to a normal state. The first potential is supplied to the first buffer circuit before the second potential is supplied to the level shifter circuit and the second buffer circuit, whereby the operations of the level shifter circuit and the second buffer circuit can be controlled. This inhibits unexpected output of a high-level signal to a wiring connected to the second buffer circuit.

公开(公告)号：US09633709B2

公开(公告)日：2017-04-25

申请号：US14718143

申请日：2015-05-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuto Yakubo ,  Shuhei Nagatsuka

IPC: G11C11/24 ,  H01L29/24 ,  H01L29/78 ,  H01L27/12 ,  H01L27/10 ,  H01L27/11 ,  G11C11/56 ,  H01L29/786 ,  H01L27/108 ,  H01L27/1156

CPC classification number: G11C11/24 ,  G11C11/5621 ,  G11C11/565 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/12 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/7869

Abstract: A highly reliable storage device with small data deterioration is provided. The storage device includes a first circuit, a second circuit, a third circuit, and a memory cell. The first circuit has a function of detecting power-on. The second circuit has a function of specifying the address of the memory cell. The third circuit has a function of refreshing the memory cell at the address specified by the second circuit after the first circuit detects power-on. The memory cell preferably includes an oxide semiconductor transistor.

公开(公告)号：US09620984B2

公开(公告)日：2017-04-11

申请号：US14208844

申请日：2014-03-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei Nagatsuka ,  Akihiro Kimura

IPC: H02J7/00 ,  H02J7/02 ,  H01M10/44 ,  H02J17/00 ,  H04B1/3883

Abstract: An electric power charge and discharge system for an electronic device having a battery, by which the electronic device can be used for a long period of time. In a wireless communication device including a wireless driving portion including a first battery and a wireless charging portion including a second battery, the first battery is charged by electric power from a fixed power supply and the second battery is charged by using electromagnetic waves existing in an external space. Further, the first battery and the second battery are discharged alternately, and during a period in which the first battery is discharged, the second battery is charged.

公开(公告)号：US09536627B2

公开(公告)日：2017-01-03

申请号：US15082431

申请日：2016-03-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki Atsumi ,  Shuhei Nagatsuka ,  Kazuaki Ohshima

IPC: G11C11/00 ,  G11C11/24 ,  G11C29/50 ,  G11C11/22

CPC classification number: G11C29/50004 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/401 ,  G11C11/4096 ,  G11C29/50016 ,  H01L27/108

Abstract: The semiconductor device includes a bit line, a transistor, a retention node, and a capacitor. The transistor has a function of charging or discharging the retention node. The capacitor has a function of retaining a potential of the retention node. A voltage greater than the sum of a writing voltage and a threshold voltage is applied to a gate of the transistor. When the transistor is turned on, a first potential is supplied to the bit line with a reference potential in a floating state. A voltage less than the sum of the writing voltage and the threshold voltage is applied to the gate of the transistor. When the transistor is turned on, a second potential is supplied to the bit line with a reference potential in a floating state. With use of the first and second potentials, the threshold voltage of the transistor is calculated without being influenced by parasitic capacitance and variations in the storage capacitance of the capacitor.

Abstract translation: 半导体器件包括位线，晶体管，保持节点和电容器。 晶体管具有对保留节点进行充电或放电的功能。 电容器具有保持保持节点的电位的功能。 大于写入电压和阈值电压之和的电压被施加到晶体管的栅极。 当晶体管导通时，第一电位以浮置状态的基准电位提供给位线。 小于写入电压和阈值电压之和的电压被施加到晶体管的栅极。 当晶体管导通时，第二电位以浮置状态的基准电位提供给位线。 利用第一和第二电位，晶体管的阈值电压被计算而不受寄生电容和电容器的存储电容的变化的影响。

公开(公告)号：US09490370B2

公开(公告)日：2016-11-08

申请号：US14873278

申请日：2015-10-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato ,  Shuhei Nagatsuka ,  Takanori Matsuzaki ,  Hiroki Inoue

IPC: H01L29/12 ,  H01L29/786 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/04 ,  H01L27/105 ,  H01L27/12 ,  H01L27/108 ,  H01L27/11 ,  H01L49/02

CPC classification number: H01L29/7869 ,  G11C16/0425 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10805 ,  H01L27/11 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/11563 ,  H01L27/11568 ,  H01L27/1225 ,  H01L28/40 ,  H01L29/78693 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792

Abstract: The semiconductor device includes a source line, a bit line, a signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line through switching elements, a second driver circuit electrically connected to the source line through a switching element, a third driver circuit electrically connected to the signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor. The second transistor includes an oxide semiconductor material.