公开(公告)号：US09851942B2

公开(公告)日：2017-12-26

申请号：US15443015

申请日：2017-02-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki Kurokawa

IPC: G06F7/00 ,  G11C5/06 ,  G06F17/00

CPC classification number: G06F7/00 ,  G06F17/00 ,  G11C5/063

Abstract: The circuit scale of a semiconductor device that can perform arithmetic processing of analog data is reduced. In the semiconductor device, a memory cell is configured to generate a first current corresponding to first analog data and to generate a second current corresponding to the first analog data and second analog data. A reference memory cell is configured to generate a reference current corresponding to reference data. A first circuit is configured to generate and hold a third current corresponding to the difference between the first current and the reference current when the first current is lower than the reference current. A second circuit is configured to generate and hold a fourth current corresponding to the difference between the first current and the reference current when the first current is higher than the reference current. One of the first circuit and the second circuit is configured to generate a fifth current corresponding to third analog data.

公开(公告)号：US09848146B2

公开(公告)日：2017-12-19

申请号：US15131284

申请日：2016-04-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki Kurokawa

IPC: H04N5/369 ,  H04N5/3745 ,  H04N5/376 ,  H04N5/232

CPC classification number: H04N5/3698 ,  H04N5/23241 ,  H04N5/37455 ,  H04N5/3765

Abstract: An imaging device with low power consumption is provided. The imaging device includes pixels and an A/D converter circuit. The pixels have a function of holding first imaging data and a function of obtaining differential data between the first imaging data and second imaging data. The A/D converter circuit includes a comparator circuit and a counter circuit. When the output of the pixels corresponds to the differential data, the supply of a clock signal to the counter circuit is stopped.

公开(公告)号：US09848144B2

公开(公告)日：2017-12-19

申请号：US14799006

申请日：2015-07-14

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yuki Okamoto ,  Munehiro Kozuma ,  Yoshiyuki Kurokawa

IPC: H04N5/363 ,  H01L27/146 ,  H04N5/357 ,  H04N5/378

CPC classification number: H04N5/363 ,  H01L27/14612 ,  H01L27/14627 ,  H01L27/14643 ,  H01L27/14665 ,  H04N5/3575 ,  H04N5/378

Abstract: A novel semiconductor device, a semiconductor device where influence of noise is lessened, or a semiconductor device with high reliability is provided. A first circuit has a function of generating an optical data signal in accordance with the amount of irradiation light and a function of generating a reset signal corresponding to a reset state of the first circuit. A second circuit has a function of controlling output of the optical data signal and the reset signal from the first circuit to a fourth circuit. A third circuit has a function of controlling generation of the reset signal to be output from the first circuit to the fourth circuit. The fourth circuit has a function of calculating the difference between the optical data signal input from the first circuit and the reset signal input from the first circuit after input of the optical data signal.

公开(公告)号：US09843308B2

公开(公告)日：2017-12-12

申请号：US15203910

申请日：2016-07-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro Kozuma ,  Yoshiyuki Kurokawa ,  Takayuki Ikeda

IPC: H03K3/03 ,  H03K3/012 ,  H03L7/099 ,  H03L7/14 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786 ,  H03B1/02

CPC classification number: H03K3/012 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/7869 ,  H03B1/02 ,  H03K3/0315 ,  H03L7/0995 ,  H03L7/14 ,  H03L2207/08

Abstract: A low-power voltage controlled oscillator is provided. The voltage controlled oscillator includes (2n+1) first circuit components (n is an integer of one or more). An output terminal of the first circuit component in a k-th stage (k is an integer of one or more and 2n or less) is connected to an input terminal of the first circuit component in a (k+1)-th stage. An output terminal of the first circuit component in a (2n+1)-th stage is connected to an input terminal of the first circuit component in a first stage. One of the first circuit components includes a second circuit component and a third circuit component whose input terminal is connected to an output terminal of the second circuit component. The third circuit component includes a first transistor and a second transistor whose source-drain resistance is controlled in accordance with a signal input to a gate through the first transistor.

公开(公告)号：US20170330531A1

公开(公告)日：2017-11-16

申请号：US15587983

申请日：2017-05-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Yoshiyuki Kurokawa

IPC: G09G5/14 ,  G09G3/3225 ,  B60K35/00

CPC classification number: G09G5/14 ,  B60K35/00 ,  B60K2370/152 ,  B60K2370/331 ,  G09G3/3225 ,  G09G2310/0232 ,  G09G2340/04 ,  G09G2340/14 ,  G09G2380/02 ,  G09G2380/10

Abstract: A display system and vehicle that have novel structures are provided. The display system includes a display panel, a correction circuit, and a memory circuit. The display panel is flexible. The display panel includes a display region and a non-display region. The memory circuit has a function of storing first data about the display region and second data about the non-display region. The non-display region has a region which overlaps with the display region when the display panel is bent. The correction circuit has a function of generating image data to be written to pixels in the display region on the basis of the first data and the second data.

公开(公告)号：US09742419B2

公开(公告)日：2017-08-22

申请号：US15151590

申请日：2016-05-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki Okamoto ,  Yoshiyuki Kurokawa

IPC: H03B5/24 ,  H03L7/099 ,  H03K3/03 ,  H03L7/093 ,  H01L27/12 ,  H01L29/786

CPC classification number: H03L7/0995 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/7869 ,  H03B5/24 ,  H03K3/0315 ,  H03L7/093 ,  H03L2207/06

Abstract: Controllability of an oscillator circuit is improved. The oscillator circuit has inverters in odd-numbered stages. A circuit is electrically connected to a power supply node of the inverters to which a high power supply potential is input. The circuit includes a first transistor, a second transistor, and a capacitor. The first transistor includes an oxide semiconductor in its channel. A holding circuit including the first transistor and the capacitor has a function of holding an analog potential that is input from the outside. The potential held by the holding circuit is input to a gate of the second transistor. A power supply potential is supplied to the inverters through the second transistor, so that the delay time of the inverter can be controlled by the potential of the gate of the second transistor.

公开(公告)号：US09679628B2

公开(公告)日：2017-06-13

申请号：US14837261

申请日：2015-08-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki Kurokawa

IPC: G11C11/402 ,  H01L29/786 ,  G11C11/34 ,  H01L27/146 ,  H01L27/1156 ,  G11C11/56 ,  H01L27/06 ,  G11C29/04 ,  H01L21/8258

CPC classification number: G11C11/402 ,  G11C11/34 ,  G11C11/565 ,  G11C2029/0403 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/1156 ,  H01L27/146 ,  H01L29/7869

Abstract: To provide a memory cell for storing multilevel data that is less likely to be affected by variations in characteristics of transistors and that is capable of easily writing multilevel data in a short time and accurately reading it out. In writing, a current corresponding to multilevel data is supplied to the transistor in the memory cell and stored as the gate-drain voltage of the transistor in the memory cell. In reading, a current is supplied to the transistor in the transistor with the stored gate-drain voltage, and the multilevel data is obtained from the voltage supplied to generate a current that is equal to the current.

公开(公告)号：US09515107B2

公开(公告)日：2016-12-06

申请号：US14986119

申请日：2015-12-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki Kurokawa ,  Takayuki Ikeda ,  Hikaru Tamura ,  Munehiro Kozuma ,  Masataka Ikeda ,  Takeshi Aoki

IPC: H04N5/355 ,  H01L27/146 ,  H01L29/786 ,  H01L31/105

CPC classification number: H01L27/14616 ,  H01L27/14603 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14643 ,  H01L29/7869 ,  H01L31/1055 ,  H04N5/361 ,  H04N5/374 ,  H04N5/378

Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.

公开(公告)号：US20160343452A1

公开(公告)日：2016-11-24

申请号：US15158860

申请日：2016-05-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takayuki Ikeda ,  Yoshiyuki Kurokawa

IPC: G11C27/02 ,  G06N99/00 ,  H01L29/786

CPC classification number: G11C27/024 ,  G06N3/0635 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/42384 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: An electronic device applicable to an artificial neuron network. The electronic device includes a first circuit, a second circuit, and first to sixth wirings. The first circuit includes a first transistor, a second transistor, and a capacitor. The second circuit includes a third transistor. A gate of the third transistor is electrically connected to the third wiring. The capacitor capacitively couples the third wiring and the gate of the second transistor. The first circuit is capable of storing a weight as an analog value. The first transistor is typically an oxide semiconductor transistor.

Abstract translation: 适用于人造神经元网络的电子设备。 电子设备包括第一电路，第二电路和第一至第六布线。 第一电路包括第一晶体管，第二晶体管和电容器。 第二电路包括第三晶体管。 第三晶体管的栅极电连接到第三布线。 电容器将第三布线和第二晶体管的栅极电容耦合。 第一电路能够将重量作为模拟值存储。 第一晶体管通常是氧化物半导体晶体管。

公开(公告)号：US09494644B2

公开(公告)日：2016-11-15

申请号：US14542859

申请日：2014-11-17

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshiyuki Kurokawa

IPC: H01L29/786 ,  G06F11/36 ,  G06F11/14 ,  G01R31/3187 ,  G01R31/3185 ,  G01R31/317

CPC classification number: G01R31/31724 ,  G01R31/31707 ,  G01R31/31723 ,  G01R31/318508 ,  G01R31/3187 ,  G06F11/1407 ,  G06F11/3636 ,  H01L29/24 ,  H01L29/78618 ,  H01L29/7869

Abstract: A semiconductor device in which the area of a circuit that is unnecessary during normal operation is small. The semiconductor device includes a first circuit and a second circuit. The first circuit includes a third circuit storing at least one pair of first data including a history of a branch instruction and a first address corresponding to the branch instruction; a fourth circuit comparing a second address of an instruction and the first address; and a fifth circuit selecting the first data of one pair among the at least one pair in accordance with a comparison result. The second circuit includes a plurality of sixth circuits having a function of generating a signal for testing operation of the first circuit in accordance with second data, and a function of storing the at least one pair together with the second circuit after the operation is tested.

Abstract translation: 在正常操作期间不需要的电路的面积小的半导体器件。 半导体器件包括第一电路和第二电路。 第一电路包括存储至少一对第一数据的第三电路，第一数据包括分支指令的历史和对应于分支指令的第一地址; 比较指令的第二地址和第一地址的第四电路; 以及第五电路，根据比较结果选择至少一对中的一对的第一数据。 第二电路包括多个第六电路，其具有根据第二数据产生用于测试第一电路的操作的信号的功能，以及在测试操作之后与第二电路一起存储至少一对的功能。