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    Depletion free polysilicon gate electrodes
    43.
    发明授权
    Depletion free polysilicon gate electrodes 有权
    无耗多晶硅栅电极

    公开(公告)号：US6090651A

    公开(公告)日：2000-07-18

    申请号：US434340

    申请日：1999-11-05

    申请人： Helmut Puchner ,  Sheldon Aronowitz ,  Gary K. Giust

    发明人： Helmut Puchner ,  Sheldon Aronowitz ,  Gary K. Giust

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823842 ,  Y10S438/929

    摘要： A method of forming a supersaturated layer on a semiconductor device, where an initial phase layer is deposited on the semiconductor device. The initial phase layer has a solid phase dopant saturation level and a liquid phase dopant saturation level, where the liquid phase dopant saturation level is greater than the solid phase dopant saturation level. A concentration of a dopant is impregnated within the initial phase layers, where the concentration of the dopant is greater than the solid phase dopant saturation level and no more than about the liquid phase dopant saturation level. The initial phase layer is annealed, without appreciably heating the semiconductor device, using an amount of energy that is high enough to liquefy the initial phase layer over a melt duration. This dissolves the dopant in the liquefied initial phase layer. The amount of energy is low enough to not appreciably gasify or ablate the initial phase layer. The liquefied initial phase layer is cooled to freeze the dissolved dopant in a supersaturated, electrically activated concentration, thereby forming the supersaturated layer. An initial phase layer of either polysilicon or amorphous silicon may be deposited over a CMOS device. After laser annealing the initial phase layer with a melt duration of no more than about 100 nanoseconds, it is transformed into a doped polysilicon gate electrode that can be patterned and further processed.

    摘要翻译： 在半导体器件上形成过饱和层的方法，其中初始相层沉积在半导体器件上。 初始相层具有固相掺杂剂饱和水平和液相掺杂剂饱和水平，其中液相掺杂剂饱和水平大于固相掺杂剂饱和水平。 掺杂剂的浓度浸渍在初始相层中，其中掺杂剂的浓度大于固相掺杂剂饱和水平并且不大于约液相掺杂剂饱和水平。 使用一定量的足够高的能量使熔融持续时间内的初始相层液化的能量，初始相层退火，而不明显地加热半导体器件。 这溶解了液化的初始相层中的掺杂剂。 能量的量足够低，不能明显地气化或消融初始相层。 液化的初始相层被冷却以使过溶化的掺杂剂以过饱和的电活化浓度冷冻，从而形成过饱和层。 多晶硅或非晶硅的初始相层可以沉积在CMOS器件上。 在熔融持续时间不超过约100纳秒的激光退火初始相层之后，将其转变成可被图案化并进一步处理的掺杂多晶硅栅电极。

    Process for forming re-entrant geometry for gate electrode of integrated circuit structure
    44.
    发明授权
    Process for forming re-entrant geometry for gate electrode of integrated circuit structure 失效
    用于形成集成电路结构的栅电极的重入几何的工艺

    公开(公告)号：US6060375A

    公开(公告)日：2000-05-09

    申请号：US690577

    申请日：1996-07-31

    申请人： Jon Owyang ,  Sheldon Aronowitz ,  James P. Kimball

    发明人： Jon Owyang ,  Sheldon Aronowitz ,  James P. Kimball

    IPC分类号： H01L21/28 ,  H01L21/3213 ,  H01L21/3215 ,  H01L29/423 ,  H01L21/302 ,  H01L21/425

    CPC分类号： H01L21/32155 ,  H01L21/28114 ,  H01L21/32137 ,  H01L29/42376

    摘要： A crystalline semiconductor gate electrode having a re-entrant geometry and a process for making same are disclosed. The novel gate electrode may be formed from a polysilicon layer on a substrate by first implanting a masked polysilicon layer with a neutral species, i.e., a species which will not introduce a dopant into the polysilicon, such as a Group IV element, e.g., silicon, or a Group VIII element, e.g., argon. The neutral species is implanted into the masked polysilicon layer at an angle to provide a tapered implanted region which undercuts one side of the length (long dimension) of the mask. The substrate may then be rotated 180.degree. and then again implanted to provide a tapered implanted region which undercuts the opposite side of the length of the mask. When gate electrodes with such re-entrant geometry are to be formed on a substrate with their long axes at right angles to one another, i.e., some lying along an X axis in the plane of the masked polysilicon layer on the substrate and others lying along a Y axis in the plane of the masked polysilicon layer on the substrate, the substrate may be rotated 90.degree., rather than 180.degree., between each implantation, and four implantations, rather than two, are performed. After the implantations, the implanted masked polysilicon layer is then subject to an etch, preferably an anisotropic etch, which will remove the unmasked implanted portions of the polysilicon layer, as well as the implanted regions beneath the mask, resulting in a gate electrode with re-entrant or tapered sidewalls, i.e., resembling an inverted trapezoid in cross-section.

    摘要翻译： 公开了一种具有凹入几何结构的晶体半导体栅电极及其制造方法。 新颖的栅电极可以由衬底上的多晶硅层形成，首先将具有中性物质的掩模多晶硅层，即不会将掺杂剂引入到多晶硅中的物质，例如IV族元素，例如硅 ，或VIII族元素，例如氩气。 将中性物质以一定角度注入到掩模多晶硅层中，以提供切割掩模长度（长尺寸）的一侧的锥形注入区域。 然后可以将衬底旋转180°，然后再次植入以提供锥形植入区域，其切割掩模长度的相对侧。 当具有这样的复数几何形状的栅电极将以其长轴彼此成直角的方式形成在衬底上时，即一些沿着衬底上的被掩膜的多晶硅层的平面中的X轴位于其上， 在衬底上的掩模多晶硅层的平面中的Y轴，衬底可以在每次注入之间旋转90度而不是180度，并且执行四次注入而不是两次。 在注入后，植入的掩膜多晶硅层然后进行蚀刻，优选是各向异性蚀刻，其将去除多晶硅层的未屏蔽的注入部分以及掩模下面的注入区域，从而形成栅电极 入口或锥形侧壁，即横截面类似倒梯形。

    Method of manufacturing semiconductor device structures utilizing predictive dopant-dopant interactions
    46.
    发明授权
    Method of manufacturing semiconductor device structures utilizing predictive dopant-dopant interactions 失效
    利用预测掺杂剂 - 掺杂剂相互作用制造半导体器件结构的方法

    公开(公告)号：US5504016A

    公开(公告)日：1996-04-02

    申请号：US323605

    申请日：1994-10-17

    申请人： Sheldon Aronowitz

    发明人： Sheldon Aronowitz

    IPC分类号： G06F17/50 ,  H01L21/265 ,  H01L21/22 ,  H01L21/66

    CPC分类号： H01L21/26513 ,  G06F17/5018 ,  H01L21/26506

    摘要： The effect of dopant-dopant interaction on diffusion in silicon for a specific set of impurities is modeled. The first step in the modeling process involved quantum chemical calculations. The connection between the atomic scale results and macroscopic behavior was made through the medium for transmission of interactions between dopants. The molecular orbitals of the lattice system comprise that medium; consequently, interactions can be transmitted, with minimal reduction in magnitude, over separations of hundreds of lattice spacings. Macroscopically, additional flux components are generated that modify the conventional expression of Fick's second law. Detailed simulation of boron and phosphorus diffusion in germanium rich regions of silicon illustrate the power of this approach to successfully model and predict the complex behavior exhibited by a particular set of interacting dopant species.

    摘要翻译： 模拟掺杂剂 - 掺杂剂相互作用对硅中扩散的影响。 建模过程的第一步涉及量子化学计算。 通过用于透射掺杂剂之间的相互作用的介质，进行原子尺度结果与宏观行为之间的连接。 晶格系统的分子轨道包括该介质; 因此，在数百个晶格间距的分离上，可以以最小的幅度减小来传输相互作用。 在宏观上，产生了修改Fick第二定律的常规表达式的额外的通量分量。 富硅富集区中硼和磷扩散的详细模拟说明了这种方法成功建模和预测了一组特定的相互作用掺杂物种呈现的复杂行为的功能。

    Method for creating barriers for copper diffusion
    50.
    发明授权
    Method for creating barriers for copper diffusion 有权
    铜扩散障碍的方法

    公开(公告)号：US07829455B2

    公开(公告)日：2010-11-09

    申请号：US11104763

    申请日：2005-04-12

    申请人： Vladimir Zubkov ,  Sheldon Aronowitz

    发明人： Vladimir Zubkov ,  Sheldon Aronowitz

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76831 ,  H01L21/76802

    摘要： A barrier layer for a semiconductor device is provided. The semiconductor device comprises a dielectric layer, an electrically conductive copper containing layer, and a barrier layer separating the dielectric layer from the copper containing layer. The barrier layer comprises a silicon oxide layer and a dopant, where the dopant is a divalent ion, which dopes the silicon oxide layer adjacent to the copper containing layer.A method of forming a barrier layer is provided. A silicon oxide layer with a surface is provided. The surface of the silicon oxide layer is doped with a divalent ion to form a barrier layer extending to the surface of the silicon oxide layer. An electrically conductive copper containing layer is formed on the surface of the barrier layer, where the barrier layer prevents diffusion of copper into the substrate.

    摘要翻译： 提供了一种用于半导体器件的阻挡层。 该半导体器件包括电介质层，导电含铜层和将电介质层与含铜层隔开的阻挡层。 阻挡层包括氧化硅层和掺杂剂，其中掺杂剂是二价离子，其掺杂与含铜层相邻的氧化硅层。 提供形成阻挡层的方法。 提供具有表面的氧化硅层。 氧化硅层的表面掺杂有二价离子以形成延伸到氧化硅层的表面的势垒层。 在阻挡层的表面上形成导电含铜层，其中阻挡层防止铜扩散到衬底中。