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    MEMORY DEVICES USING A PLURALITY OF DIODES AS PROGRAM SELECTORS FOR MEMORY CELLS
    41.
    发明申请
    MEMORY DEVICES USING A PLURALITY OF DIODES AS PROGRAM SELECTORS FOR MEMORY CELLS 有权
    使用多个二极管作为存储器单元的程序选择器的存储器件

    公开(公告)号：US20120044736A1

    公开(公告)日：2012-02-23

    申请号：US13026783

    申请日：2011-02-14

    Applicant: Shine C. Chung

    Inventor： Shine C. Chung

    IPC: G11C5/08 ,  G11C5/06

    CPC classification number: H01L27/2436 ,  G11C8/14 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C17/16 ,  G11C17/165 ,  G11C2013/0073 ,  G11C2213/72 ,  G11C2213/74 ,  H01L27/224 ,  H01L27/2409 ,  H01L29/785 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146

    Abstract: At least one junction diode fabricated in standard CMOS logic processes can be used as program selectors for the memory cells that can be programmed based on the directions of current flow. These memory cells are MRAM, RRAM, CBRAM, or other memory cells that have a resistive element coupled to the P terminal of the first diode and to the N terminal of a second diode. The diodes can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diodes. By applying a high voltage to a resistive element and switching the N terminal of the first diode to a low voltage while disabling the second diode, a current flows through the memory cell can change the resistance into one state. Similarly, by applying a low voltage to a resistive element and switching the P terminal of the second diode to a high voltage while disabling the first diode, a current flows through the memory cell can change the resistance into another state. The P+ active region of the diode can be isolated from the N+ active region in an N well by using dummy MOS gate, SBL, or STI isolations.

    Abstract translation: 以标准CMOS逻辑工艺制造的至少一个结二极管可用作可根据电流方向编程的存储器单元的程序选择器。 这些存储单元是具有耦合到第一二极管的P端和第二二极管的N端的电阻元件的MRAM，RRAM，CBRAM或其它存储单元。 二极管可以由N阱上的P +和N +有源区域构成，作为二极管的P和N端子。 通过向电阻元件施加高电压并且在禁用第二二极管的同时将第一二极管的N端切换到低电压，流过存储器单元的电流可以将电阻改变成一个状态。 类似地，通过对电阻元件施加低电压并且在禁用第一二极管的同时将第二二极管的P端子切换到高电压，流经存储器单元的电流可将电阻改变为另一状态。 通过使用虚拟MOS栅极，SBL或STI隔离，二极管的P +有源区可以与N阱中的N +有源区隔离。

    Circuit and System of Aggregated Area Anti-Fuse in CMOS Processes
    42.
    发明申请
    Circuit and System of Aggregated Area Anti-Fuse in CMOS Processes 有权
    CMOS工艺中聚合面积保险丝的电路和系统

    公开(公告)号：US20120039107A1

    公开(公告)日：2012-02-16

    申请号：US13072783

    申请日：2011-03-28

    Applicant: Shine C. Chung

    Inventor： Shine C. Chung

    IPC: G11C17/12

    CPC classification number: G11C17/12 ,  H01L23/5252 ,  H01L27/0629 ,  H01L27/101 ,  H01L29/1083 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Gate oxide breakdown anti-fuse suffers notorious soft breakdown that reduces yield and reliability. This invention discloses circuit and system to enhance electrical field by blocking LDD so that the electrical field is higher and more focused near the drain junction, to make electrical field in the channel more uniform by creating slight conductive or conductive in part or all of the channel, or to neutralize excess carriers piled up in the oxide by applying alternative polarity pulses. The embodiments can be applied in part, all, or any combinations, depending on needs. This invention can be embodied as a 2 T anti-fuse cell having an access and a program MOS with drain area in the program MOS, or 1.5 T anti-fuse cell without any drain in the program MOS. Similarly this invention can also be embodied as a 1 T anti-fuse cell having a portion of the channel made conductive or slightly conductive to merge the access and program MOS into one device with drain area, or 0.5 T anti-fuse cell without any drain.

    Abstract translation: 栅极氧化物分解抗熔丝遭受臭名昭着的软击穿，从而降低产量和可靠性。 本发明公开了通过阻挡LDD来增强电场的电路和系统，使得电场在漏极结附近更高和更集中，以通过在部分或全部通道中产生轻微的导电或导电来使通道中的电场更均匀 或通过施加替代的极性脉冲来中和堆积在氧化物中的过量载体。 可以根据需要部分，全部或任何组合应用实施例。 本发明可以实现为具有访问的2T反熔丝单元和在编程MOS中具有漏极区的编程MOS或在程序MOS中没有任何漏极的1.5T反熔丝单元。 类似地，本发明也可以被实施为具有通道的一部分导通或稍微导电的1T反熔丝电池，以将访问和编程MOS合并成具有漏极区的一个器件，或没有任何漏极的0.5T反熔丝电池 。

    Low power read operation for programmable resistive memories
    43.
    发明授权
    Low power read operation for programmable resistive memories 有权

    公开(公告)号：US10535413B2

    公开(公告)日：2020-01-14

    申请号：US15953422

    申请日：2018-04-14

    Applicant: Shine C. Chung

    Inventor： Shine C. Chung

    IPC: G11C11/16 ,  G11C17/18 ,  G11C17/16 ,  G11C16/04 ,  G11C16/28 ,  G11C13/00 ,  G11C11/22

    Abstract: A programmable resistive memory has a plurality of programmable resistive devices (PRD) and at least one sensing circuit. The at least one of the programmable resistive device can include at least one programmable resistive element (PRE). The sensing circuit can include one PRD unit and a reference unit. Each unit has at least one capacitor to charge to a second supply voltage line and to discharge to the first supply voltage line through the PRE and the reference element, respectively. The capacitors are also coupled to comparators to monitor discharging voltages with respect to a reference voltage. By comparing the time difference when the comparators change their outputs, the magnitude of the PRE resistance with respect to the reference element resistance can be determined and converted into logic states.

    Low-pin-count non-volatile memory interface with soft programming capability
    45.
    发明授权
    Low-pin-count non-volatile memory interface with soft programming capability 有权
    具有软编程能力的低引脚数非易失性存储器接口

    公开(公告)号：US09076513B2

    公开(公告)日：2015-07-07

    申请号：US14231404

    申请日：2014-03-31

    Applicant: Shine C. Chung

    Inventor： Shine C. Chung

    IPC: G11C11/00 ,  G11C17/16 ,  G11C8/18 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32

    CPC classification number: G11C17/18 ,  G11C7/10 ,  G11C8/18 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/0408 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C17/00 ,  G11C17/146 ,  G11C17/16 ,  G11C29/022 ,  G11C29/027 ,  G11C29/1201 ,  G11C29/46 ,  G11C2216/30

    Abstract: A low-pin-count non-volatile (NVM) memory with no more than two control signals that can at least program NVM cells, load data to be programmed into output registers, or read the NVM cells. At least one of the NVM cells has at least one NVM element coupled to at least one selector and to a first supply voltage line. The selector is coupled to a second supply voltage line and having a select signal. At least one of the selected NVM cells can be coupled to at least one output register. No more than two control signals can be used to select the at least one NVM cells in the NVM sequentially for programming the data into the at least one NVM cells or loading data into the at least one output registers controlled by the pulse of the first signal and voltage level and/or timing of the second signal. Programming into the NVM cells, or loading data into output registers, can be determined by the voltage levels of the first to the second supply voltage lines. Reading at least one of the NVM cells can be activated by a third signal or by detecting ramping of the first or the second supply voltage line.

    Abstract translation: 具有不超过两个控制信号的低引脚数非易失性（NVM）存储器，可以至少编程NVM单元，将要编程的数据加载到输出寄存器中，或读取NVM单元。 至少一个NVM单元具有耦合到至少一个选择器和第一电源电压线的至少一个NVM元件。 选择器耦合到第二电源电压线并且具有选择信号。 所选择的NVM单元中的至少一个可以耦合到至少一个输出寄存器。 可以使用不超过两个控制信号来选择NVM中的至少一个NVM单元以将数据编程到至少一个NVM单元中，或者将数据加载到由第一信号的脉冲控制的至少一个输出寄存器中 和第二信号的电压电平和/或定时。 可以通过第一至第二电源电压线的电压电平来确定对NVM单元的编程或将数据加载到输出寄存器中。 读取至少一个NVM单元可以被第三信号激活或通过检测第一或第二电源电压线的斜坡。

    Low-Pin-Count Non-Volatile Memory Interface for 3D IC
    47.
    发明申请
    Low-Pin-Count Non-Volatile Memory Interface for 3D IC 有权
    3D IC的低引脚数非易失性存储器接口

    公开(公告)号：US20150009743A1

    公开(公告)日：2015-01-08

    申请号：US14493069

    申请日：2014-09-22

    Applicant: Shine C. Chung

    Inventor： Shine C. Chung

    IPC: G11C17/16 ,  G11C29/00

    CPC classification number: G11C17/16 ,  G11C8/18 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C29/028 ,  G11C29/78 ,  G11C2029/4402 ,  G11C2216/30

    Abstract: A low-pin-count non-volatile (NVM) memory to be provided in an integrated circuit for a 3D IC to repair defects, trim devices, or adjust parameters is presented here. At least one die in a 3D IC can be built with at least one low-pin-count OTP memory. The low-pin-count OTP memory can be built with a serial interface such as I2C-like or SPI-like of interface. The pins of the low-pin-count OTP in at least one dies can be coupled together to have only one set of low-pin-count bus for external access. With proper device ID, each dies in a 3D IC can be accessed individually for soft programming, programming, erasing, or reading. This technique can improve the manufacture yield, device, circuit, or logic performance or to store configuration parameters for customization after 3D IC are built.

    Abstract translation: 这里介绍了在用于3D IC的集成电路中提供的用于修复缺陷，修整装置或调整参数的低引脚数非易失性（NVM）存储器。 至少可以使用至少一个低引脚数OTP内存来构建3D IC中的至少一个裸片。 低引脚数OTP存储器可以使用类似I2C或类似接口的串行接口来构建。 至少一个管芯中的低引脚数OTP的引脚可以耦合在一起，以便只有一组用于外部访问的低引脚数总线。 使用适当的器件ID，可以单独访问3D IC中的每个管芯，以进行软编程，编程，擦除或读取。 该技术可以提高制造产量，器件，电路或逻辑性能，或者在构建3D IC后存储用于定制的配置参数。

    ONE-TIME PROGRAMMABLE DEVICES USING JUNCTION DIODE AS PROGRAM SELECTOR FOR ELECTRICAL FUSES WITH EXTENDED AREA
    48.
    发明申请
    ONE-TIME PROGRAMMABLE DEVICES USING JUNCTION DIODE AS PROGRAM SELECTOR FOR ELECTRICAL FUSES WITH EXTENDED AREA 审中-公开
    使用连接二极管的一次性可编程器件作为具有扩展区域的电熔丝的程序选择器

    公开(公告)号：US20150003143A1

    公开(公告)日：2015-01-01

    申请号：US14485698

    申请日：2014-09-13

    Applicant: Shine C. Chung

    Inventor： Shine C. Chung

    IPC: G11C17/16 ,  H01L27/10

    CPC classification number: G11C17/16 ,  G11C13/0002 ,  G11C13/004 ,  G11C17/146 ,  G11C17/165 ,  G11C29/027 ,  G11C2013/0054 ,  H01L27/10 ,  H01L27/224 ,  H01L27/228 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

    Abstract: Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuses. At least one portion of the electrical fuse can have at least one extended area to accelerate programming. An extended area is an extension of the fuse element beyond contact or via longer than required by design rules. The extended area also has reduced or substantially no current flowing through. The program selector can be at least one MOS. The OTP device can have the at least one OTP element coupled to at least one diode in a memory cell.

    Abstract translation: 以标准CMOS逻辑处理器制造的结二极管可用作一次性可编程（OTP）器件（例如电气保险丝）的程序选择器。 电熔丝的至少一部分可以具有至少一个扩展区域以加速编程。 扩展区域是保险丝元件延伸超出接触点或通过比设计规则要求更长的延伸区域。 扩展区域也具有减少或基本上没有电流流过。 节目选择器可以是至少一个MOS。 OTP设备可以具有耦合到存储器单元中的至少一个二极管的至少一个OTP元件。

    CIRCUIT AND SYSTEM FOR CONCURRENTLY PROGRAMMING MULTIPLE BITS OF OTP MEMORY DEVICES
    50.
    发明申请
    CIRCUIT AND SYSTEM FOR CONCURRENTLY PROGRAMMING MULTIPLE BITS OF OTP MEMORY DEVICES 有权
    用于同时编程OTP存储器件的多个位的电路和系统

    公开(公告)号：US20140269135A1

    公开(公告)日：2014-09-18

    申请号：US14085228

    申请日：2013-11-20

    Applicant: Shine C. Chung

    Inventor： Shine C. Chung

    IPC: G11C17/16 ,  G11C17/14

    CPC classification number: G11C17/16 ,  G11C8/14 ,  G11C13/0002 ,  G11C13/0069 ,  G11C17/14 ,  G11C17/146 ,  G11C17/165 ,  G11C17/18 ,  G11C2013/0085 ,  G11C2013/0088

    Abstract: Circuits and systems for concurrently programming a plurality of OTP cells in an OTP memory are disclosed. Each OTP cell can have an electrical fuse element coupled a program selector having a control terminal. The control terminals of a plurality of OTP cells can be coupled to a plurality of local wordlines, and a plurality of the local wordlines can be coupled to at least one global wordline. A plurality of banks of bitlines can have each bitline coupled to a plurality of the OTP cells via the control terminal of the program selector. A plurality of bank selects can enable turning on the wordlines or bitlines in a bank. A plurality of the OTP cells can be configured to be programmable concurrently into a different logic state by applying voltages to at least one selected global wordline and at least one selected bitline to a plurality of the selected OTP cells in a plurality of banks, if a plurality of banks are enabled.

    Abstract translation: 公开了用于同时编程OTP存储器中的多个OTP单元的电路和系统。 每个OTP单元可以具有耦合到具有控制端子的程序选择器的电熔丝元件。 多个OTP单元的控制终端可以耦合到多个本地字线，并且多个本地字线可以耦合到至少一个全局字线。 多个位线组可以经由程序选择器的控制端将每个位线耦合到多个OTP单元。 多个银行选择可以使得能够打开银行中的字线或位线。 多个OTP单元可以被配置为通过向多个银行中的多个所选择的OTP单元施加电压到至少一个所选择的全局字线和至少一个选定的位线来并行地编程成不同的逻辑状态，如果 启用多个银行。

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