公开(公告)号：US09959927B2

公开(公告)日：2018-05-01

申请号：US15404087

申请日：2017-01-11

Applicant: Silicon Storage Technology, Inc. ,  Agency For Science, Technology And Research

Inventor： Feng Zhou ,  Xian Liu ,  Nhan Do ,  Hieu Van Tran ,  Hung Quoc Nguyen ,  Mark Reiten ,  Zhixian Chen ,  Wang Xinpeng ,  Guo-Qiang Lo

IPC: G11C16/04 ,  G11C13/00 ,  H01L45/00

CPC classification number: G11C13/0007 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16

Abstract: A memory device and method comprising a metal oxide material disposed between and in electrical contact with first and second conductive electrodes, and a voltage source configured to apply a plurality of voltage pulses spaced apart in time across the first and second electrodes. For each one of the voltage pulses, an amplitude of the voltage increases during the voltage pulse.

公开(公告)号：US20180033482A1

公开(公告)日：2018-02-01

申请号：US15597709

申请日：2017-05-17

Applicant: Silicon Storage Technology, Inc. ,  Agency For Science, Technology, and Research

Inventor： Santosh Hariharan ,  Hieu Van Tran ,  Feng Zhou ,  Xian Liu ,  Steven Lemke ,  Nhan Do ,  Zhixian Chen ,  Xinpeng Wang

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

CPC classification number: G11C13/0011 ,  G11C11/00 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/0078 ,  G11C2013/0083 ,  G11C2013/0088 ,  G11C2013/0092 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/085 ,  H01L45/146

Abstract: A memory device includes a metal oxide material disposed between and in electrical contact with first and second conductive electrodes, and an electrical current source configured to apply one or more electrical current pulses through the metal oxide material. For each of the one or more electrical current pulses, an amplitude of the electrical current increases over time during the electrical current pulse to form a conductive filament in metal oxide material.

公开(公告)号：US09882033B2

公开(公告)日：2018-01-30

申请号：US15368451

申请日：2016-12-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Nhan Do

IPC: G11C11/34 ,  H01L29/792 ,  H01L21/3205 ,  H01L29/788 ,  H01L29/66 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/423 ,  H01L21/02

CPC classification number: H01L29/66833 ,  H01L21/0217 ,  H01L27/1052 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/7926

Abstract: A memory cell formed by forming a trench in the surface of a substrate. First and second spaced apart regions are formed in the substrate with a channel region therebetween. The first region is formed under the trench. The channel region includes a first portion that extends along a sidewall of the trench and a second portion that extends along the surface of the substrate. A charge trapping layer in the trench is adjacent to and insulated from the first portion of the channel region for controlling the conduction of the channel region first portion. An electrically conductive gate in the trench is adjacent to and insulated from the charge trapping layer and from the first region and is capacitively coupled to the charge trapping layer. An electrically conductive control gate is disposed over and insulated from the second portion of the channel region for controlling its conduction.

公开(公告)号：US20170337971A1

公开(公告)日：2017-11-23

申请号：US15593231

申请日：2017-05-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/14

CPC classification number: G11C16/14 ,  G11C16/0425 ,  G11C16/10

Abstract: A memory device and method of erasing same that includes a substrate of semiconductor material and a plurality of memory cells formed on the substrate and arranged in an array of rows and columns. Each of the memory cells includes spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region, a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and a program-erase gate disposed over and insulated from the source region. The program-erase gate lines alone or in combination with the select gate lines, or the source lines, are arranged in the column direction so that each memory cell can be individually programmed, read and erased.

公开(公告)号：US09793280B2

公开(公告)日：2017-10-17

申请号：US15057590

申请日：2016-03-01

Applicant: Silicon Storage Technology, Inc.

Inventor： Chun-Ming Chen ,  Jeng-Wei Yang ,  Chien-Sheng Su ,  Man-Tang Wu ,  Nhan Do

IPC: H01L29/66 ,  H01L27/11531 ,  H01L29/423 ,  H01L21/28 ,  H01L27/11534 ,  G11C16/04

CPC classification number: H01L27/11531 ,  G11C16/0425 ,  H01L21/28273 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/66825

Abstract: A memory device and method including a semiconductor substrate with memory and logic device areas. A plurality of memory cells are formed in the memory area, each including first source and drain regions with a first channel region therebetween, a floating gate disposed over a first portion of the first channel region, a control gate disposed over the floating gate, a select gate disposed over a second portion of the first channel region, and an erase gate disposed over the source region. A plurality of logic devices formed in the logic device area, each including second source and drain regions with a second channel region therebetween, and a logic gate disposed over the second channel region. The substrate upper surface is recessed lower in the memory area than in the logic device area, so that the taller memory cells have an upper height similar to that of the logic devices.

公开(公告)号：US20170179141A1

公开(公告)日：2017-06-22

申请号：US15453829

申请日：2017-03-08

Applicant: Silicon Storage Technology, Inc.

Inventor： Chien-Sheng Su ,  Jeng-Wei Yang ,  Man-Tang Wu ,  Chun-Ming Chen ,  Hieu Van Tran ,  Nhan Do

IPC: H01L27/11521 ,  H01L29/788 ,  H01L29/08 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/1052 ,  H01L27/11551 ,  H01L29/0847 ,  H01L29/42328 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7856 ,  H01L29/7881

Abstract: A non-volatile memory cell, and method of making, that includes a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between. A conductive floating gate includes a first portion extending along a first portion of the top surface, and second and third portions extending along first portions of the two side surfaces, respectively. A conductive control gate includes a first portion extending along a second portion of the top surface, second and third portions extending along second portions of the two side surfaces respectively, a fourth portion extending up and over at least some of the floating gate first portion, and fifth and sixth portions extending out and over at least some of the floating gate second and third portions respectively.

公开(公告)号：US09633735B2

公开(公告)日：2017-04-25

申请号：US14486687

申请日：2014-09-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Nhan Do ,  Yuri Tkachev ,  Kai Man Yue ,  Xiaozhou Qian ,  Ning Bai

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/12 ,  G11C29/02

CPC classification number: G11C16/14 ,  G11C16/0425 ,  G11C16/12 ,  G11C16/16 ,  G11C29/021 ,  G11C29/028

Abstract: A system and method to inhibit the erasing of a portion of a sector of split gate flash memory cells while allowing the remainder of the sector to be erased is disclosed. The inhibiting is controlled by control logic that applies one or more bias voltages to the portion of the sector whose erasure is to be inhibited.

公开(公告)号：US20170110194A1

公开(公告)日：2017-04-20

申请号：US15244947

申请日：2016-08-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Vipin Tiwari ,  Nhan Do

IPC: G11C16/12 ,  G11C16/26 ,  G11C16/30 ,  G11C16/14

CPC classification number: G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  H01L27/11582 ,  H01L28/00

Abstract: A memory device, and method of operation, includes an array of non-volatile memory cells and a controller. The controller is configured to perform an operation (e.g. erase, program, etc.) on a first plurality of the non-volatile memory cells using operational voltages with a first energy margin, and perform the same operation on a second plurality of the non-volatile memory cells using operational voltages with a second energy margin that is greater than the first energy margin. The operations of varying energy margins are based on the required storage longevity of the data being stored (lower energy margins for data being stored for shorter periods of time) to save energy and wear.

公开(公告)号：US09548380B2

公开(公告)日：2017-01-17

申请号：US13829111

申请日：2013-03-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Nhan Do

IPC: G11C11/34 ,  H01L29/792 ,  H01L21/3205 ,  H01L29/788 ,  H01L29/66 ,  H01L27/105 ,  H01L29/423 ,  H01L27/115

CPC classification number: H01L29/66833 ,  H01L21/0217 ,  H01L27/1052 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/7926

Abstract: A memory cell formed by forming a trench in the surface of a substrate. First and second spaced apart regions are formed in the substrate with a channel region therebetween. The first region is formed under the trench. The channel region includes a first portion that extends along a sidewall of the trench and a second portion that extends along the surface of the substrate. A charge trapping layer in the trench is adjacent to and insulated from the first portion of the channel region for controlling the conduction of the channel region first portion. An electrically conductive gate in the trench is adjacent to and insulated from the charge trapping layer and from the first region and is capacitively coupled to the charge trapping layer. An electrically conductive control gate is disposed over and insulated from the second portion of the channel region for controlling its conduction.

Abstract translation: 通过在衬底表面形成沟槽形成的存储单元。 第一和第二间隔开的区域形成在衬底中，其间具有通道区域。 第一区域形成在沟槽下方。 沟道区域包括沿着沟槽的侧壁延伸的第一部分和沿衬底的表面延伸的第二部分。 沟槽中的电荷捕获层与沟道区的第一部分相邻并与其绝缘，用于控制沟道区第一部分的导通。 沟槽中的导电栅极与电荷俘获层相邻并且与第一区绝缘，并与电荷捕获层电容耦合。 导电控制栅极设置在沟道区域的第二部分上并与沟道区域的第二部分绝缘，用于控制其导通。

公开(公告)号：US20160133639A1

公开(公告)日：2016-05-12

申请号：US14935201

申请日：2015-11-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Nhan Do

IPC: H01L27/115 ,  G11C16/14 ,  G11C16/26 ,  G11C16/04

CPC classification number: H01L27/11526 ,  G11C16/0408 ,  G11C16/14 ,  G11C16/26 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/7881

Abstract: A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates. For each of the pairs of memory cells, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region.

Abstract translation: 一种存储器件，具有每个具有单个连续沟道区的存储单元对，在沟道区的第一和第二部分上的第一和第二浮置栅极，位于第一和第二沟道区域之间的沟道区的第三部分上的擦除栅极， 以及第一和第二浮动栅极上的第一和第二控制栅极。 对于每对存储器单元，第一区域电连接到相同有源区域中相邻的一对存储器单元的第二区域，并且第二区域电连接到相邻存储器对的第一区域 细胞在相同的活性区域。