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206 条记录 (耗时 0.043 秒)

    Clock multiplexing system
    43.
    发明授权
    Clock multiplexing system 有权
    时钟复用系统

    公开(公告)号：US07071756B1

    公开(公告)日：2006-07-04

    申请号：US10837329

    申请日：2004-04-30

    申请人： Vasisht Mantra Vadi ,  Steven P. Young

    发明人： Vasisht Mantra Vadi ,  Steven P. Young

    IPC分类号： G06F1/04 ,  H03K3/00

    CPC分类号： G06F1/04 ,  H03K17/005 ,  H03K17/693

    摘要： A clock control circuit in an integrated circuit for providing a differential clock signal to a differential clock tree. The clock control circuit includes: first differential multiplexers configured to select first outputs from the input clock signals; second differential multiplexers coupled to the first differential multiplexers and configured to select second outputs from the first outputs; loop back signal lines configured to feed back the second outputs to at least part of the input clock signals of the first differential multiplexers; and differential signal lines of the differential clock tree coupled to the second outputs.

    摘要翻译： 用于向差分时钟树提供差分时钟信号的集成电路中的时钟控制电路。 时钟控制电路包括：第一差分复用器，被配置为从输入时钟信号中选择第一输出; 第二差分多路复用器，耦合到所述第一差分多路复用器，并且被配置为从所述第一输出中选择第二输出; 配置为将所述第二输出反馈到所述第一差分多路复用器的输入时钟信号的至少一部分的环回信号线; 以及差分时钟树的差分信号线耦合到第二输出。

    Structures and methods of testing interconnect structures in programmable logic devices
    45.
    发明授权
    Structures and methods of testing interconnect structures in programmable logic devices 有权
    在可编程逻辑器件中测试互连结构的结构和方法

    公开(公告)号：US06933747B1

    公开(公告)日：2005-08-23

    申请号：US10684183

    申请日：2003-10-10

    申请人： Trevor J. Bauer ,  Steven P. Young ,  Ramakrishna K. Tanikella

    发明人： Trevor J. Bauer ,  Steven P. Young ,  Ramakrishna K. Tanikella

    IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/17764 ,  G01R31/2853 ,  G01R31/31723 ,  G01R31/318516 ,  H03K19/17736

    摘要： Structures enabling the efficient testing of interconnect in programmable logic devices (PLDS), and methods utilizing these structures. A PLD includes a non-homogeneous array of programmable logic blocks and an array of standardized interconnect blocks, where the same interconnect block is used for different types of logic blocks. Coupled between each of the interconnect blocks and the associated logic block is a standardized test structure, allowing the same test configuration to be used for each interconnect block even though the interconnect blocks are associated with logic blocks of different types. In some embodiments, one or more types of logic blocks are not associated with standardized test structures. These logic blocks are coupled directly to their associated interconnect blocks, and are preferably of a type that can be configured to emulate the standardized test structure. Thus, by a correct application of configuration data all of the interconnect blocks display the same behavior.

    摘要翻译： 能够对可编程逻辑器件（PLDS）中的互连进行有效测试的结构以及利用这些结构的方法。 PLD包括可编程逻辑块的非均匀阵列和标准化互连块阵列，其中相同的互连块用于不同类型的逻辑块。 在每个互连块和相关联的逻辑块之间耦合是标准化的测试结构，允许将相同的测试配置用于每个互连块，即使互连块与不同类型的逻辑块相关联。 在一些实施例中，一个或多个类型的逻辑块不与标准化测试结构相关联。 这些逻辑块直接耦合到它们相关联的互连块，并且优选地是可被配置为模拟标准化测试结构的类型。 因此，通过配置数据的正确应用，所有互连块都显示相同的行为。

    Carry logic design having simplified timing modeling for a field programmable gate array
    46.
    发明授权
    Carry logic design having simplified timing modeling for a field programmable gate array 有权
    进行逻辑设计具有简化的现场可编程门阵列的时序建模

    公开(公告)号：US06847228B1

    公开(公告)日：2005-01-25

    申请号：US10300212

    申请日：2002-11-19

    申请人： Patrick J. Crotty ,  Tao Pi ,  Steven P. Young

    发明人： Patrick J. Crotty ,  Tao Pi ,  Steven P. Young

    IPC分类号： G06F7/507 ,  H03K19/173 ,  G06F7/50

    CPC分类号： G06F7/507 ,  H03K19/1737

    摘要： A configurable logic block (CLB) slice is provided that includes a single path for a carry input signal to propagate through the CLB slice as a carry output signal. This single path includes a multiplexer that is configured to receive the input signals (including the carry input signal) and provides an output signal that can be routed as the carry output signal. A driver circuit can be coupled to the output terminal of the multiplexer, thereby improving the drive of the single path. A separate path is provided in parallel with the first multiplexer path, thereby enabling the carry input signal to be applied to exclusive OR gates within the CLB slice, or to be provided as an intermediate carry output signal. The single path provides a relatively fast and consistent manner of routing the carry input signal through the CLB slice as the carry output signal. The first and second paths accommodate a carry initialization signal as well as an intermediate carry input signal.

    摘要翻译： 提供了可配置逻辑块（CLB）片，其包括用于进位输入信号作为进位输出信号传播通过CLB片的单个路径。 该单路径包括被配置为接收输入信号（包括进位输入信号）并且提供可作为进位输出信号路由的输出信号的多路复用器。 驱动器电路可以耦合到多路复用器的输出端，从而改善单路径的驱动。 提供与第一多路复用器路径并行的单独路径，从而使携带输入信号能够施加到CLB切片内的异或门，或者被提供为中间进位输出信号。 单路提供了一种相对快速和一致的方式，将进位输入信号通过CLB切片作为进位输出信号。 第一和第二路径容纳进位初始化信号以及中间进位输入信号。

    Methods for aligning data and clock signals
    47.
    发明授权
    Methods for aligning data and clock signals 有权
    数据和时钟信号对齐的方法

    公开(公告)号：US06798241B1

    公开(公告)日：2004-09-28

    申请号：US10376522

    申请日：2003-02-27

    申请人： Trevor J. Bauer ,  Steven P. Young ,  Christopher D. Ebeling ,  Jason R. Bergendahl ,  Arthur J. Behiel

    发明人： Trevor J. Bauer ,  Steven P. Young ,  Christopher D. Ebeling ,  Jason R. Bergendahl ,  Arthur J. Behiel

    IPC分类号： H03K19173

    CPC分类号： H03K5/135 ,  H04L7/0337

    摘要： Described are methods and circuits for aligning data and clock signals. Methods in accordance with some embodiments separate incoming data into three differently timed data signals: an early signal, an intermediate signal, and a late signal. The timing of the three data signals can be collectively moved with respect to the clock signal. In addition, the temporal spacing between the three signals can be adjusted so that the early and late signals define a window encompassing the intermediate signal. The three signals are aligned with respect to the clock edge to center the intermediate data signal on the clock edge. The early and late signals can be monitored to identify changes in the relative timing of the clock and data signals. Some embodiments automatically alter the timing of the data and/or clock signals to keep the intermediate data signal centered on the clock edge.

    摘要翻译： 描述了用于对准数据和时钟信号的方法和电路。 根据一些实施例的方法将输入数据分成三个不同时间的数据信号：早期信号，中间信号和后期信号。 三个数据信号的定时可以相对于时钟信号共同移动。 此外，可以调整三个信号之间的时间间隔，使得早期和晚期信号限定包围中间信号的窗口。 三个信号相对于时钟边沿对齐，以使中间数据信号在时钟边沿居中。 可以监视早期和晚期信号以识别时钟和数据信号的相对定时的变化。 一些实施例自动改变数据和/或时钟信号的定时，以使中间数据信号以时钟边缘为中心。

    Method and apparatus for incorporating a multiplier into an FPGA
    48.
    发明授权
    Method and apparatus for incorporating a multiplier into an FPGA 有权
    将乘法器并入到FPGA中的方法和装置

    公开(公告)号：US06362650B1

    公开(公告)日：2002-03-26

    申请号：US09574714

    申请日：2000-05-18

    申请人： Bernard J. New ,  Steven P. Young

    发明人： Bernard J. New ,  Steven P. Young

    IPC分类号： H03K19177

    CPC分类号： G06F15/7867 ,  G06F7/523 ,  G06F17/5054 ,  H03K19/17732 ,  H03K19/1776

    摘要： One or more columns of multi-function tiles are positioned between CLB tiles of the FPGA array. Each multi-function tile includes multiple function elements that share routing resources. In one embodiment, a multi-function tile includes a configurable, dual-ported RAM and a multiplier that share routing resources of the multi-function tile. The RAM includes first and second input ports coupled to first and second input data buses, respectively, and includes first and second output ports coupled to first and second output data buses, respectively. The multiplier includes first and second operand ports coupled to receive operands from the first and second input data buses, and in response thereto provides a product. In one embodiment, the most significant bits (MSBs) of the product are selectively provided to the first output data bus using bus multiplexer logic, and the least significant bits (LSBs) of the product are selectively provided to the second output data bus using bus multiplexer logic.

    摘要翻译： 一列或多列多功能瓦片位于FPGA阵列的CLB瓦片之间。 每个多功能瓦片包括共享路由资源的多个功能元件。 在一个实施例中，多功能瓦片包括可配置的双端口RAM和共享多功能瓦片的路由资源的乘法器。 RAM包括分别耦合到第一和第二输入数据总线的第一和第二输入端口，并且分别包括耦合到第一和第二输出数据总线的第一和第二输出端口。 乘法器包括耦合以从第一和第二输入数据总线接收操作数的第一和第二操作数端口，并且响应于此提供产品。 在一个实施例中，使用总线复用器逻辑将产品的最高有效位（MSB）选择性地提供给第一输出数据总线，并且使用总线选择性地将产品的最低有效位（LSB）提供给第二输出数据总线 多路复用逻辑

    FPGA architecture with dual-port deep look-up table RAMS
    49.
    发明授权
    FPGA architecture with dual-port deep look-up table RAMS 有权
    具有双端口深度查询表RAMS的FPGA架构

    公开(公告)号：US06297665B1

    公开(公告)日：2001-10-02

    申请号：US09574445

    申请日：2000-05-19

    申请人： Trevor J. Bauer ,  Steven P. Young

    发明人： Trevor J. Bauer ,  Steven P. Young

    IPC分类号： H03K19177

    CPC分类号： H03K19/1736 ,  G11C19/00 ,  H03K19/17736 ,  H03K19/1776

    摘要： A configurable logic block (CLB) having a plurality of identical configurable logic element (CLE) slices is provided. Each CLE slice includes a plurality of function generators (lookup tables) that can be configured to form a random access memory (RAM). The width and depth of the RAM are selectable by controlling the routing of signals within the CLE slices. A hierarchy of wide function multiplexers (F5, F6, and F7 multiplexers) are provided to selectively route read data values from the lookup tables. Another set of multiplexers is used to selectively route write data values to the lookup tables. These multiplexers can be configured to provide a single write data value to all of the lookup tables to form a deep RAM. Alternatively, these multiplexers can be configured to provide one write data value to half of the lookup tables, and another write data value to the other half of the lookup tables. This pattern repeats down to the level where these multiplexers can be configured to provide a different write data value to each of the lookup tables. A write control circuit is also provided in each CLE slice to provide write enable signals to the lookup tables in a manner consistent with the selected RAM size. Read and write addresses are provided in a manner that enables the CLB to be operated as a dual-port RAM having selectable width and depth.

    摘要翻译： 提供具有多个相同可配置逻辑元件（CLE）片的可配置逻辑块（CLB）。 每个CLE切片包括可被配置成形成随机存取存储器（RAM）的多个功能发生器（查找表）。 通过控制CLE切片内信号的路由可以选择RAM的宽度和深度。 提供了多功能多路复用器（F5，F6和F7多路复用器）的层次结构，用于选择性地从查找表路由读取数据值。 另一组多路复用器用于选择性地将写入数据值路由到查找表。 这些多路复用器可以被配置为向所有查找表提供单个写数据值以形成深RAM。 或者，这些多路复用器可以被配置为向查找表的一半提供一个写入数据值，并将另一个写入数据值提供给查找表的另一半。 该模式重复到这些复用器可被配置为向每个查找表提供不同的写入数据值的级别。 在每个CLE片中还提供写入控制电路，以与所选择的RAM大小一致的方式向查找表提供写使能信号。 提供读写地址，使得CLB能够作为具有可选宽度和深度的双端口RAM来操作。

    Block RAM with reset to user selected value
    50.
    发明授权
    Block RAM with reset to user selected value 有权
    将RAM重置为用户选择的值

    公开(公告)号：US06282127B1

    公开(公告)日：2001-08-28

    申请号：US09625672

    申请日：2000-07-24

    申请人： Raymond C. Pang ,  Steven P. Young ,  Trevor J. Bauer

    发明人： Raymond C. Pang ,  Steven P. Young ,  Trevor J. Bauer

    IPC分类号： G11C700

    CPC分类号： G11C7/1051 ,  G11C7/1057

    摘要： A RAM block includes a circuit for causing the RAM to provide a reset value on the output or a previously captured output value from the RAM when a Reset signal is active. The Reset signal does not change the RAM contents but causes all outputs of the block RAM to be either a reset value or a capture value, as selected by the user. This is useful when the RAM block is configured as a state machine. Thus, in an FPGA or other programmable device, an application can start the state machine in a known state with all address bits equal to 0 and can reset the state machine to this startup state. When the reset signal is active, the state machine can feed back the reset value or capture value to the address inputs of the RAM block that receive state feedback data, regardless of the data actually in those locations.

    摘要翻译： RAM块包括用于当复位信号有效时使RAM在输出上提供复位值或从RAM提供先前捕获的输出值的电路。 复位信号不会更改RAM内容，但会导致块RAM的所有输出为用户选择的复位值或捕捉值。 当RAM块被配置为状态机时，这是有用的。 因此，在FPGA或其他可编程器件中，应用程序可以在所有地址位等于0的已知状态下启动状态机，并可将状态机复位到该启动状态。 当复位信号有效时，状态机可以将接收状态反馈数据的复位值或捕获值反馈给RAM块的地址输入，无论这些位置中的数据如何。