公开(公告)号：US20240421045A1

公开(公告)日：2024-12-19

申请号：US18816698

申请日：2024-08-27

Applicant: Texas Instruments Incorporated

Inventor： Christopher Daniel Manack ,  Nazila Dadvand ,  Salvatore Pavone

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/49 ,  H01L23/492 ,  H01L23/532

Abstract: A microelectronic device is formed by thinning a substrate of the microelectronic device from a die attach surface of the substrate, and forming a copper-containing layer on the die attach surface of the substrate. A protective metal layer is formed on the copper-containing layer. Subsequently, the copper-containing layer is attached to a package member having a package die mount area. The protective metal layer may optionally be removed prior to attaching the copper-containing layer to the package member. Alternatively, the protective metal layer may be left on the copper-containing layer when the copper-containing layer is attached to the package member. A structure formed by the method is also disclosed.

公开(公告)号：US12142586B2

公开(公告)日：2024-11-12

申请号：US17809854

申请日：2022-06-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vivek Swaminathan Sridharan ,  Christopher Daniel Manack ,  Joseph Liu

IPC: H01L23/00

Abstract: In some examples, a chip scale package (CSP) comprises a semiconductor die; a passivation layer abutting the semiconductor die; a via extending through the passivation layer; and a first metal layer abutting the via. The CSP also includes an insulation layer abutting the first metal layer, with the insulation layer having an orifice with a maximal horizontal area of less than 32400 microns2. The CSP further includes a second metal layer abutting the insulation layer and adapted to couple to a solder ball. The second metal layer abuts the first metal layer at a point of contact defined by the orifice in the insulation layer.

公开(公告)号：US12068221B2

公开(公告)日：2024-08-20

申请号：US16985103

申请日：2020-08-04

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

IPC: H01L23/373 ,  C23C14/16 ,  C23C18/38 ,  C25D3/38 ,  C25D3/46 ,  H01L21/285 ,  H01L21/288 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L23/3736 ,  C23C14/165 ,  C23C18/38 ,  C25D3/38 ,  C25D3/46 ,  H01L21/2855 ,  H01L21/288 ,  H01L21/76873 ,  H01L21/78

Abstract: Described examples include a process that includes forming a diffusion barrier layer on a backside of a semiconductor wafer. The process also includes forming a seed copper layer on the diffusion barrier layer. The process also includes forming a copper layer on the seed copper layer. The process also includes immersion plating a silver layer on the copper layer.

公开(公告)号：US11942386B2

公开(公告)日：2024-03-26

申请号：US17001429

申请日：2020-08-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christopher Daniel Manack ,  Patrick Francis Thompson ,  Qiao Chen

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L23/315 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49575 ,  H01L24/02 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/48465 ,  H01L2224/73207 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/07025 ,  H01L2924/19104

Abstract: In examples, a semiconductor device comprises a semiconductor package including a mold compound covering a semiconductor die. The semiconductor package has a surface and a cavity formed in the surface. The semiconductor device comprises an electronic device positioned within the cavity, the electronic device coupled to the semiconductor die via a conductive terminal extending through the mold compound.

公开(公告)号：US11869820B2

公开(公告)日：2024-01-09

申请号：US17810568

申请日：2022-07-01

Applicant: Texas Instruments Incorporated

Inventor： Amit Sureshkumar Nangia ,  Sreenivasan Kalyani Koduri ,  Siva Prakash Gurrum ,  Christopher Daniel Manack

IPC: H01L23/00 ,  H01L23/16

CPC classification number: H01L23/16 ,  H01L24/97 ,  H01L2224/73265 ,  H01L2924/14

Abstract: An integrated circuit (IC) includes a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion, with at least a portion of nodes in the circuitry electrically coupled to bond pads provided by a top metal layer. A metal wall that is ring-shaped is positioned above the top metal layer that is not electrically coupled to the circuitry. The stress sensitive circuit portion is with at least a majority of its area within an inner area of the substrate that is framed by the metal wall to provide a cavity.

公开(公告)号：US11837518B2

公开(公告)日：2023-12-05

申请号：US17003382

申请日：2020-08-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Todd Wyant ,  Matthew John Sherbin ,  Christopher Daniel Manack ,  Patrick Francis Thompson ,  You Chye How

IPC: H01L23/31 ,  H01L23/552 ,  H01L21/56 ,  H01L21/78 ,  H01L21/683

CPC classification number: H01L23/3185 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3171 ,  H01L23/552 ,  H01L21/6836 ,  H01L2221/68336

Abstract: In examples, a chip scale package (CSP) comprises a semiconductor die; a conductive terminal coupled to the semiconductor die; and a non-conductive coat covering a backside of the semiconductor die and a sidewall of the semiconductor die. The non-conductive coat has a thickness of less than 45 microns.

公开(公告)号：US20230352373A1

公开(公告)日：2023-11-02

申请号：US18297751

申请日：2023-04-10

Applicant: Texas Instruments Incorporated

Inventor： Christopher Daniel Manack ,  Sreenivasan Kalyani Koduri

IPC: H01L23/495 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/4952 ,  H01L21/565 ,  H01L23/49575 ,  H01L23/49513 ,  H01L21/4825 ,  H01L23/3114 ,  H01L23/49527

Abstract: In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions; at least one semiconductor device die over the die mount portion of the package substrate, the semiconductor device die having bond pads on an active surface facing away from the package substrate; electrical connections between at least one of the bond pads and one of the lead portions; a post interconnect over at least one of the bond pads, the post interconnect extending away from the active surface of the semiconductor device die; and a dielectric material covering a portion of the package substrate, the semiconductor device die, a portion of the post interconnect, and the electrical connections, forming a packaged semiconductor device, wherein the post interconnect extends through the dielectric material and had an end facing away from the semiconductor device die that is exposed from the dielectric material.

公开(公告)号：US11587858B2

公开(公告)日：2023-02-21

申请号：US17323939

申请日：2021-05-18

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/495 ,  B23K1/00 ,  C25D5/12 ,  C25D5/18 ,  C25D7/12 ,  C25D3/22 ,  B23K101/36 ,  C25D3/12

Abstract: A microelectronic device has bump bond structures on input/output (I/O) pads. The bump bond structures include copper-containing pillars, a barrier layer including cobalt and zinc on the copper-containing pillars, and tin-containing solder on the barrier layer. The barrier layer includes 0.1 weight percent to 50 weight percent cobalt and an amount of zinc equivalent to a layer of pure zinc 0.05 microns to 0.5 microns thick. A lead frame has a copper-containing member with a similar barrier layer in an area for a solder joint. Methods of forming the microelectronic device are disclosed.

公开(公告)号：US11562949B2

公开(公告)日：2023-01-24

申请号：US16904193

申请日：2020-06-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Patrick Francis Thompson ,  Christopher Daniel Manack ,  Madison Paige Koziol

IPC: H01L23/495 ,  H01L23/34 ,  H01L23/48 ,  H01L21/00 ,  H05K7/04 ,  H05K7/18 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/28

Abstract: A semiconductor package includes a semiconductor die with an active surface and an inactive surface, the active surface including metal pillars providing electrical connections to functional circuitry of the semiconductor die, and a backside metal layer on the inactive surface. The backside metal layer is attached to the inactive surface. The semiconductor package further includes a plurality of leads with each of the leads including an internal leadfinger portion and an exposed portion that includes a bonding portion. Distal ends of the metal pillars are in contact with and electrically coupled to the internal leadfinger portions. The backside metal layer is exposed on an outer surface of the semiconductor package. The bonding portions and the backside metal layer approximately planar to each other.

公开(公告)号：US11387155B2

公开(公告)日：2022-07-12

申请号：US16859530

申请日：2020-04-27

Applicant: Texas Instruments Incorporated

Inventor： Amit Sureshkumar Nangia ,  Sreenivasan Kalyani Koduri ,  Siva Prakash Gurrum ,  Christopher Daniel Manack

IPC: H01L23/16 ,  H01L23/00

Abstract: An integrated circuit (IC) includes a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion, with at least a portion of nodes in the circuitry electrically coupled to bond pads provided by a top metal layer. A metal wall that is ring-shaped is positioned above the top metal layer that is not electrically coupled to the circuitry. The stress sensitive circuit portion is with at least a majority of its area within an inner area of the substrate that is framed by the metal wall to provide a cavity.