公开(公告)号：US20180226920A1

公开(公告)日：2018-08-09

申请号：US15427856

申请日：2017-02-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Subhashish Mukherjee ,  Kumar Anurag Shrivastava ,  Sreeram Subramanyam Nasum

IPC: H03B5/12 ,  H03H1/00 ,  H03H7/01 ,  H01L23/00 ,  H01L23/31 ,  H01L23/64 ,  H01L25/07

Abstract: Apparatus for communication across a capacitively coupled channel are disclosed herein. An example circuit includes a first plate substantially parallel to a substrate, thereby forming a first capacitance intermediate the first plate and the substrate. A second plate is substantially parallel to the substrate and the first plate, the first plate intermediate the substrate and the second plate. A third plate is substantially parallel to the substrate, thereby forming a second capacitance intermediate the third plate and the substrate. A fourth plate is substantially parallel to the substrate and the third plate, the third plate intermediate the substrate and the fourth plate. An inductor is connected to the first plate and the third plate, the inductor to, in combination with the first capacitance and the second capacitance, form an LC amplifier.

公开(公告)号：US10014844B1

公开(公告)日：2018-07-03

申请号：US15395353

申请日：2016-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kumar Anurag Shrivastava ,  Subhashish Mukherjee ,  Madhulatha Bonu

IPC: H04B1/04 ,  H03H9/54 ,  H03H11/28 ,  H03F3/193 ,  H04B1/40

Abstract: A circuit includes an amplifier having an input that receives an alternating current (AC) waveform and an output that is coupled to a power source via a bias resistor. A bulk acoustic wave (BAW) resonator is coupled in parallel to the bias resistor via the power source and the amplifier output. The BAW resonator and the amplifier output forms a band pass filter to filter the AC waveform received at the amplifier input and to provide a filtered AC waveform at the amplifier output.

公开(公告)号：US09893916B2

公开(公告)日：2018-02-13

申请号：US15200706

申请日：2016-07-01

Applicant: Texas Instruments Incorporated

Inventor： Subhashish Mukherjee ,  Abhijit Anant Patki ,  Madhulatha Bonu ,  Kumar Anurag Shrivastava

IPC: H04L7/00 ,  H04L27/22 ,  H03L7/087 ,  H03L7/113 ,  H03K19/21 ,  H04L7/033

CPC classification number: H04L27/22 ,  H03D3/00 ,  H03K19/21 ,  H03L7/081 ,  H03L7/087 ,  H03L7/113 ,  H04L7/0087 ,  H04L7/0331 ,  H04L27/2271

Abstract: Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase; when the data signal is oscillating at the first phase, output a first logic value; and when the data signal is oscillating at the second phase, output a second logic value, the output of the fast phase change detection circuit being used to determine whether the first output signal or the second output signal will be utilized in the feedback loop of the low bandwidth phase lock loop.

公开(公告)号：US20160315670A1

公开(公告)日：2016-10-27

申请号：US15199611

申请日：2016-06-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Subhashish Mukherjee ,  Anoop Bhat ,  Kumar Anurag Shrivastava

IPC: H04B5/00 ,  H04L27/04

CPC classification number: H04B5/0087 ,  H04B5/0031 ,  H04L27/04

Abstract: In described examples, a method of inductive coupled communications includes providing a first resonant tank (first tank) and a second resonant tank (second tank) tuned to essentially the same resonant frequency, each having antenna coils and switches positioned for changing a Q and a bandwidth of their tank. The antenna coils are separated by a distance that provides near-field communications. The first tank is driven to for generating induced oscillations to transmit a predetermined number of carrier frequency cycles providing data. After the predetermined number of cycles, a switch is activated for widening the bandwidth of the first tank. Responsive to the oscillations in the first tank, the second tank begins induced oscillations. Upon detecting a bit associated with the induced oscillations, a switch is activated for widening the bandwidth of the second tank and a receiver circuit receiving an output of the second tank is reset.

Abstract translation: 在所描述的实例中，电感耦合通信的方法包括提供调谐到基本上相同谐振频率的第一谐振槽（第一箱）和第二谐振槽（第二箱），每个共振频率具有定位用于改变Q和A的天线线圈和开关 他们的坦克的带宽。 天线线圈分开一个提供近场通信的距离。 驱动第一坦克用于产生感应振荡以传送提供数据的预定数量的载波频率周期。 在预定数量的循环之后，启动开关以扩大第一箱的带宽。 响应于第一个罐中的振荡，第二个罐开始诱发振荡。 在检测到与感应振荡相关联的位时，启动开关用于加宽第二箱的带宽，并且接收接收第二箱的输出的接收器电路被复位。

公开(公告)号：US20160112006A1

公开(公告)日：2016-04-21

申请号：US14518001

申请日：2014-10-20

Applicant: Texas Instruments Incorporated

Inventor： Gireesh Rajendran ,  Rakesh Kumar ,  Subhashish Mukherjee ,  Ashish Lachhwani

IPC: H03B5/12

CPC classification number: H03B5/1212 ,  H03B5/1228 ,  H03B5/1265

Abstract: Low noise switchable varactors and digital controlled oscillator (DCO) circuitry are presented for creating alternating signals at controlled frequencies, including a first transistor for selectively coupling two capacitors between varactor output nodes when a control signal is in a first state, second and third transistors for selectively coupling first and second internal nodes between the respective capacitors and the first transistor with a third internal node when the control signal is in the first state, and an inverter disconnected from the first and second internal nodes to mitigate phase noise and operable to control the voltage of the third internal node according to the control signal.

Abstract translation: 提供了低噪声可切换变容二极管和数字控制振荡器（DCO）电路，用于在受控频率下产生交变信号，包括用于在控制信号处于第一状态时选择性地耦合变容二极管输出节点之间的两个电容器的第一晶体管，第二和第三晶体管 当控制信号处于第一状态时，选择性地将相应电容器和第一晶体管之间的第一和第二内部节点耦合到第三内部节点，并且逆变器从第一和第二内部节点断开以减轻相位噪声并且可操作地控制 根据控制信号，第三内部节点的电压。

公开(公告)号：US20140357186A1

公开(公告)日：2014-12-04

申请号：US14289895

申请日：2014-05-29

Applicant: Texas Instruments Incorporated

Inventor： Subhashish Mukherjee ,  Venugopal Gopinathan

IPC: H04B5/00

CPC classification number: H04B5/0093 ,  H01L23/645 ,  H01L23/66 ,  H01L2223/6677 ,  H03B5/08 ,  H04B5/0075

Abstract: In apparatus for die-to-die communication, a first die includes at least a first circuit, and a second die includes at least a second circuit. The first die is separated by a fixed distance from the second die. In response to a signal, the first circuit is configured to induce a current in the second circuit via a magnetic coupling between the first circuit and the second circuit.

Abstract translation: 在管芯到管芯通信的装置中，第一管芯至少包括第一电路，第二管芯至少包括第二电路。 第一模具与第二模具分开一定距离。 响应于信号，第一电路被配置为通过第一电路和第二电路之间的磁耦合在第二电路中感应电流。

公开(公告)号：US20240113722A1

公开(公告)日：2024-04-04

申请号：US18534861

申请日：2023-12-11

Applicant: Texas Instruments Incorporated

Inventor： Jayawardan Janardhanan ,  Yogesh Darwhekar ,  Subhashish Mukherjee

IPC: H03M1/10

CPC classification number: H03M1/1014

Abstract: A system includes a first digital-to-time converter (DTC) adapted to receive a first DTC code and a first clock signal. The first DTC provides an output clock signal. The system includes a calibration DTC adapted to receive a calibration DTC code and a second clock signal. The calibration DTC provides a calibration output signal. The system includes a latch comparator which provides outputs indicative of which of the output clock signal and the calibration output signal is received first. The system includes an average computation module which provides an average value of the outputs of the latch comparator. The system includes a digital controller adapted to receive the average value. The digital controller provides the DTC code and the calibration DTC code.

公开(公告)号：US20230013907A1

公开(公告)日：2023-01-19

申请号：US17377698

申请日：2021-07-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Subhashish Mukherjee ,  Jayawardan Janardhanan ,  Yogesh Darwhekar

IPC: H03M1/10 ,  H03K5/135 ,  G04F10/00

Abstract: A digital-to-time converter (DTC) and methods of calibrating the same reduces or mitigates nonlinearity and thus improves DTC performance. A slope of a voltage signal of the DTC is calibrated using a capacitor and a comparator. Capacitance of the capacitor and/or maximum current of a current source is adjusted to configure the comparator to output a signal during a second phase when a reference voltage signal is at or above a first level and below a second level. Calibrating gain of the DTC includes adjusting a time difference between an output signal of the DTC set at a first digital code value and the output signal of the DTC set at a second digital code value to be one period of a clock signal input to the DTC. Calibrating integral nonlinearity of the DTC includes measuring a time period for each of multiple digital code values of the DTC.

公开(公告)号：US11515209B2

公开(公告)日：2022-11-29

申请号：US16773692

申请日：2020-01-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Subhashish Mukherjee ,  Raja Selvaraj ,  Venugopal Gopinathan

IPC: H01L21/78 ,  H01L23/58 ,  H01L23/66 ,  H01L23/18 ,  H01L29/06 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L49/02

Abstract: An example integrated circuit die includes: lower level conductor layers, lower level insulator layers between the lower level conductor layers, lower level vias extending vertically through the lower level insulator layers, upper level conductor layers overlying the lower level conductor layers, upper level insulator layers between and surrounding the upper level conductor layers, upper level vias; at least two scribe seals arranged to form a vertical barrier extending vertically from the semiconductor substrate to a passivation layer at an upper surface of the integrated circuit die; and at least one opening extending vertically through one of the at least two scribe seals and extending through: the upper level conductor layers, the upper level via layers, the lower level conductor layers, and the lower level via layers.

公开(公告)号：US11500336B1

公开(公告)日：2022-11-15

申请号：US17317628

申请日：2021-05-11

Applicant: Texas Instruments Incorporated

Inventor： Yogesh Darwhekar ,  Subhashish Mukherjee ,  Narala Raghavendra Reddy

IPC: H03M1/50 ,  G04F10/00 ,  G06F1/08 ,  H03M3/00 ,  G04G3/02

Abstract: An example digital to time converter includes: a first switch having a first terminal, a second terminal, and a first control terminal configured to receive a control signal. A second switch having a third terminal coupled to second terminal, a fourth terminal, and a second control terminal configured to receive a divided clock signal. A third switch having a fifth terminal coupled to the second terminal and the third terminal, a sixth terminal, and a third control terminal configured to receive an inverted version of divided clock signal. A fourth switch having a seventh terminal coupled to the second terminal, an eighth terminal, and a fourth control terminal configured to receive an inverted version of control signal. A fifth switch having a ninth terminal coupled to the eighth terminal and a fifth control terminal configured to receive the inverted divided clock signal. A capacitor coupled to the sixth terminal.