公开(公告)号：US09837487B2

公开(公告)日：2017-12-05

申请号：US14954524

申请日：2015-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lin ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L21/70 ,  H01L29/06 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0607 ,  H01L21/28264 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

公开(公告)号：US20170170067A1

公开(公告)日：2017-06-15

申请号：US14968913

申请日：2015-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ruei Yeh ,  Wen-Hsin Chan ,  Kang-Min Kuo

IPC: H01L21/768 ,  H01L23/535 ,  H01L21/306 ,  H01L21/308 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L21/76897 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3085 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/535 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/78

Abstract: Provided is a semiconductor device including a substrate, a gate structure, a dielectric layer, an etch stop layer, and an adhesion layer. The gate structure is formed over the substrate. The dielectric layer is formed aside the gate structure. The adhesion layer overlays a top surface of the gate structure and extends to a first top surface of the dielectric layer. The etch stop layer is over the adhesion layer and in contact with a second top surface of the dielectric layer.

公开(公告)号：US09633941B2

公开(公告)日：2017-04-25

申请号：US14832655

申请日：2015-08-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shu-Cheng Lin ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/76877 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate. The first dielectric layer has a first opening exposing the first conductive structure. The semiconductor device structure includes a seal layer covering an inner wall of the first opening and in direct contact with the first dielectric layer. The seal layer includes a dielectric material including an oxygen compound. The semiconductor device structure includes a second conductive structure filled in the first opening and surrounded by the seal layer. The second conductive structure is electrically connected to the first conductive structure.

公开(公告)号：US09349688B2

公开(公告)日：2016-05-24

申请号：US14791555

申请日：2015-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Chieh Liao ,  Han-Wei Yang ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L23/482 ,  H01L23/522 ,  H01L29/40 ,  H01L23/31 ,  H01L23/29

CPC classification number: H01L23/3171 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/291 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/4824 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/564 ,  H01L29/401 ,  H01L29/41 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having enhanced passivation integrity is disclosed. The device includes a substrate, a first layer, and a metal layer. The first layer is formed over the substrate. The first layer includes a via opening and a tapered portion proximate to the via opening. The metal layer is formed over the via opening and the tapered portion of the first layer. The metal layer is substantially free from gaps and voids.

公开(公告)号：US09299621B2

公开(公告)日：2016-03-29

申请号：US14024688

申请日：2013-09-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Wei Yang ,  Yi-Ruei Lin ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC: H01L23/544 ,  H01L21/66 ,  H01L27/088

CPC classification number: H01L22/14 ,  H01L22/12 ,  H01L22/30 ,  H01L22/34 ,  H01L27/088 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

Abstract: An integrated circuit includes a number of lateral diffusion measurement structures arranged on a silicon substrate. A lateral diffusion measurement structure includes a p-type region and an n-type region which cooperatively span a predetermined initial distance between opposing outer edges of the lateral diffusion measurement structure. The p-type and n-type regions meet at a p-n junction expected to be positioned at a target junction location after dopant diffusion has occurred.

Abstract translation: 集成电路包括布置在硅衬底上的多个横向扩散测量结构。 横向扩散测量结构包括p型区域和n型区域，其协作地跨越横向扩散测量结构的相对外边缘之间的预定初始距离。 在发生掺杂剂扩散之后，p型和n型区域在预期位于目标连接位置处的p-n结处相交。

公开(公告)号：US20150311156A1

公开(公告)日：2015-10-29

申请号：US14791555

申请日：2015-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Chieh Liao ,  Han-Wei Yang ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC: H01L23/528 ,  H01L23/31 ,  H01L23/29 ,  H01L23/522

CPC classification number: H01L23/3171 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/291 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/4824 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/564 ,  H01L29/401 ,  H01L29/41 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having enhanced passivation integrity is disclosed. The device includes a substrate, a first layer, and a metal layer. The first layer is formed over the substrate. The first layer includes a via opening and a tapered portion proximate to the via opening. The metal layer is formed over the via opening and the tapered portion of the first layer. The metal layer is substantially free from gaps and voids.

Abstract translation: 公开了一种具有增强的钝化完整性的半导体器件。 该器件包括衬底，第一层和金属层。 第一层形成在衬底上。 第一层包括通孔开口和靠近通孔开口的锥形部分。 金属层形成在通孔开口和第一层的锥形部分之上。 金属层基本上没有间隙和空隙。

公开(公告)号：US09070687B2

公开(公告)日：2015-06-30

申请号：US13930161

申请日：2013-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Chung Lai ,  Kang-Min Kuo ,  Yen-Ming Peng ,  Gwo-Chyuan Kuoh ,  Han-Wei Yang ,  Yi-Ruei Lin ,  Chin-Chia Chang ,  Ying-Chieh Liao ,  Che-Chia Hsu ,  Bor-Zen Tien

IPC: H01L23/52 ,  H01L23/525 ,  H01L21/306

CPC classification number: H01L23/5256 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/306 ,  H01L21/32136 ,  H01L21/563 ,  H01L21/76202 ,  H01L21/76224 ,  H01L23/3171 ,  H01L29/0649 ,  H01L29/167 ,  H01L29/66477 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device with the metal fuse is provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which is grounded. The protection of the metal fuse can be designed to start at the beginning of the metallization formation processes. The grounded dummy feature provides a path for the plasma charging to the ground during the entire back end of the line process. The metal fuse is a process level protection as opposed to the diode, which is a circuit level protection. As a process level protection, the metal fuse protects subsequently-formed circuitry. In addition, no additional active area is required for the metal fuse in the chip other than internal dummy patterns that are already implemented.

Abstract translation: 提供具有金属保险丝的半导体器件。 金属熔断器连接电子部件（例如，晶体管）和接地的现有虚拟特征。 金属保险丝的保护可以设计为在金属化形成工艺开始时开始。 接地的虚拟特征提供了在线路过程的整个后端期间等离子体对地面充电的路径。 金属保险丝是与二极管相反的过程电平保护，这是电路级保护。 作为工艺级保护，金属保险丝保护随后形成的电路。 此外，除了已经实现的内部虚拟图案之外，芯片中的金属熔断器不需要额外的有源区域。

公开(公告)号：US20150054163A1

公开(公告)日：2015-02-26

申请号：US13974400

申请日：2013-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Chieh Liao ,  Han-Wei Yang ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L23/3171 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/291 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/4824 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/564 ,  H01L29/401 ,  H01L29/41 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having enhanced passivation integrity is disclosed. The device includes a substrate, a first layer, and a metal layer. The first layer is formed over the substrate. The first layer includes a via opening and a tapered portion proximate to the via opening. The metal layer is formed over the via opening and the tapered portion of the first layer. The metal layer is substantially free from gaps and voids.

Abstract translation: 公开了一种具有增强的钝化完整性的半导体器件。 该器件包括衬底，第一层和金属层。 第一层形成在衬底上。 第一层包括通孔开口和靠近通孔开口的锥形部分。 金属层形成在通孔开口和第一层的锥形部分之上。 金属层基本上没有间隙和空隙。

公开(公告)号：US20150048507A1

公开(公告)日：2015-02-19

申请号：US13965294

申请日：2013-08-13

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Chin-Chia Chang ,  Han-Wei Yang ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC: H01L23/532 ,  H01L21/265

CPC classification number: H01L21/265 ,  H01L21/26513 ,  H01L21/76286 ,  H01L21/823814 ,  H01L27/0629 ,  H01L27/1463 ,  H01L29/6659 ,  H01L29/7833

Abstract: An integrated circuit includes a p-type region formed beneath a surface of a semiconductor substrate, and an n-type region formed beneath the surface of the semiconductor substrate. The n-type region meets the p-type region at a p-n junction. A diffusion barrier structure, which is beneath the surface of the semiconductor substrate and extends along a side of the p-n junction, limits lateral diffusion between the p-type region and n-type region.

Abstract translation: 集成电路包括形成在半导体衬底的表面下方的p型区域和形成在半导体衬底的表面下方的n型区域。 n型区域在p-n结处与p型区域相遇。 在半导体衬底的表面下方并且沿着p-n结的一侧延伸的扩散阻挡结构限制了p型区域和n型区域之间的横向扩散。

公开(公告)号：US20230378253A1

公开(公告)日：2023-11-23

申请号：US18358399

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lin ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/0607 ,  H01L29/7848 ,  H01L21/28264 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.