公开(公告)号：US20210083114A1

公开(公告)日：2021-03-18

申请号：US16572320

申请日：2019-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsun Wang ,  Chen-Ming Lee ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Pei-Yu Chou ,  Kuo-Ju Chen

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/764 ,  H01L29/417 ,  H01L21/762 ,  H01L27/088

Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.

公开(公告)号：US10510891B1

公开(公告)日：2019-12-17

申请号：US16504670

申请日：2019-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Kuo-Ju Chen ,  Chun-Hung Wu ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Ying-Lang Wang

IPC: H01L21/3115 ,  H01L21/02 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L21/3215 ,  H01L21/8234 ,  H01L29/165

Abstract: Embodiments disclosed herein relate generally to forming an ultra-shallow junction having high dopant concentration and low contact resistance in a p-type source/drain region. In an embodiment, a method includes forming a source/drain region in an active area on a substrate, the source/drain region comprising germanium, performing an ion implantation process using gallium (Ga) to form an amorphous region in the source/drain region, performing an ion implantation process using a dopant into the amorphous region, and subjecting the amorphous region to a thermal process.

公开(公告)号：US20190378928A1

公开(公告)日：2019-12-12

申请号：US16504670

申请日：2019-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Kuo-Ju Chen ,  Chun-Hung Wu ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Ying-Lang Wang

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/3115 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/3215

Abstract: Embodiments disclosed herein relate generally to forming an ultra-shallow junction having high dopant concentration and low contact resistance in a p-type source/drain region. In an embodiment, a method includes forming a source/drain region in an active area on a substrate, the source/drain region comprising germanium, performing an ion implantation process using gallium (Ga) to form an amorphous region in the source/drain region, performing an ion implantation process using a dopant into the amorphous region, and subjecting the amorphous region to a thermal process.

公开(公告)号：US10347762B1

公开(公告)日：2019-07-09

申请号：US15991570

申请日：2018-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Kuo-Ju Chen ,  Chun-Hung Wu ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Ying-Lang Wang

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3115 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/165 ,  H01L21/3215

Abstract: Embodiments disclosed herein relate generally to forming an ultra-shallow junction having high dopant concentration and low contact resistance in a p-type source/drain region. In an embodiment, a method includes forming a source/drain region in an active area on a substrate, the source/drain region comprising germanium, performing an ion implantation process using gallium (Ga) to form an amorphous region in the source/drain region, performing an ion implantation process using a dopant into the amorphous region, and subjecting the amorphous region to a thermal process.

公开(公告)号：US12278141B2

公开(公告)日：2025-04-15

申请号：US17675462

申请日：2022-02-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ju Chen ,  Shih-Hsiang Chiu ,  Meng-Han Chou ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/76 ,  H01L21/31 ,  H01L21/3115 ,  H01L21/768

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices are described herein. A method includes implanting neutral elements into a dielectric layer, an etch stop layer, and a metal feature, the dielectric layer being disposed over the etch stop layer and the metal feature being disposed through the dielectric layer and the etch stop layer. The method further includes using a germanium gas as a source for the neutral elements and using a beam current above 6.75 mA to implant the neutral elements.

公开(公告)号：US20240387661A1

公开(公告)日：2024-11-21

申请号：US18786082

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ju Chen ,  Shih-Hsiang Chiu ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/417 ,  H01L21/285 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material including a material different from the first contact material, a first portion of the second contact material further including the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, a first portion of the dielectric liner including the first dopant.

公开(公告)号：US20240363399A1

公开(公告)日：2024-10-31

申请号：US18771016

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ju Chen ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo ,  Meng-Han Chou

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/78

CPC classification number: H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L29/785

Abstract: A method includes forming a first dielectric layer over a source/drain region, and forming a source/drain contact plug over and electrically connecting to the source/drain region. A top portion of the source/drain contact plug has a first lateral dimension. An implantation process is performed to implant a dopant into the first dielectric layer. The implantation process results in the source/drain contact plug to have a second lateral dimension smaller than the first lateral dimension. The method further includes forming a second dielectric layer over the etch stop layer, and forming a gate contact plug adjacent to the source/drain contact plug.

公开(公告)号：US12068195B2

公开(公告)日：2024-08-20

申请号：US18330466

申请日：2023-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Chieh Wu ,  Tang-Kuei Chang ,  Kuo-Hsiu Wei ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Su-Hao Liu ,  Kuo-Ju Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Ting-Kui Chang ,  Chia Hsuan Lee

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3115 ,  H01L23/485 ,  H01L23/532

CPC classification number: H01L21/76883 ,  H01L21/76825 ,  H01L23/5226 ,  H01L21/31155 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/485 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/00 ,  H01L2924/0002

Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.

公开(公告)号：US12015055B2

公开(公告)日：2024-06-18

申请号：US18350838

申请日：2023-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Huicheng Chang ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Kuo-Ju Chen ,  Chun-Hung Wu ,  Chang-Miao Liu ,  Huai-Tei Yang ,  Lun-Kuang Tan ,  Wei-Ming You

IPC: H01L29/08 ,  H01L21/02 ,  H01L21/265 ,  H01L21/285 ,  H01L29/167 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/26513 ,  H01L21/28518 ,  H01L29/167 ,  H01L29/41791 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

公开(公告)号：US11955553B2

公开(公告)日：2024-04-09

申请号：US18174045

申请日：2023-02-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Kuo-Ju Chen ,  Wen-Yen Chen ,  Ying-Lang Wang ,  Liang-Yin Chen ,  Li-Ting Wang ,  Huicheng Chang

IPC: H01L21/24 ,  H01L21/02 ,  H01L21/324 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L21/02694 ,  H01L21/324 ,  H01L21/76829 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6681

Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.