公开(公告)号：US11532586B2

公开(公告)日：2022-12-20

申请号：US16587568

申请日：2019-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Jen Tseng ,  Wei-Yu Chen ,  Ting-Wei Chiang ,  Li-Chun Tien

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/528 ,  H01L25/00 ,  H01L21/768 ,  H01L23/48 ,  H01L21/822 ,  H01L27/06 ,  H01L23/535 ,  H01L21/74 ,  H01L25/07 ,  H01L27/118 ,  H01L23/522 ,  H01L23/532

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a first device tier including a first semiconductor substrate having a first plurality of devices. A second semiconductor substrate is formed over the first device tier. A first conductive layer is formed within the second semiconductor substrate, and a second conductive layer is formed within the second semiconductor substrate and over the first conductive layer. The first conductive layer and the second conductive layer have different patterns as viewed from a top-view. A second plurality of devices are formed on the second semiconductor substrate. The first and second conductive layers are configured to electrically couple the first plurality of devices and the second plurality of devices.

公开(公告)号：US11482491B2

公开(公告)日：2022-10-25

申请号：US15877398

申请日：2018-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  Chih-Hua Chen ,  Ching-Hua Hsieh ,  Hsiu-Jen Lin ,  Yu-Chih Huang ,  Yu-Peng Tsai ,  Chia-Shen Cheng ,  Chih-Chiang Tsao ,  Jen-Jui Yu

IPC: H01L23/528 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/522 ,  H01L23/538 ,  H01L21/683

Abstract: A package structure includes an insulating encapsulation, at least one die, and conductive structures. The at least one die is encapsulated in the insulating encapsulation. The conductive structures are located aside of the at least one die and surrounded by the insulating encapsulation, and at least one of the conductive structures is electrically connected to the at least one die. Each of the conductive structures has a first surface, a second surface opposite to the first surface and a slant sidewall connecting the first surface and the second surface, and each of the conductive structures has a top diameter greater than a bottom diameter thereof, and wherein each of the conductive structures has a plurality of pores distributed therein.

公开(公告)号：US11469218B2

公开(公告)日：2022-10-11

申请号：US17073888

申请日：2020-10-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  An-Jhih Su ,  Wei-Yu Chen ,  Ying-Ju Chen ,  Tsung-Shu Lin ,  Chin-Chuan Chang ,  Hsien-Wei Chen ,  Wei-Cheng Wu ,  Li-Hsien Huang ,  Chi-Hsi Wu ,  Der-Chyang Yeh

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

Abstract: A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.

公开(公告)号：US20220285171A1

公开(公告)日：2022-09-08

申请号：US17664458

申请日：2022-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsien-Wei Chen ,  Chi-Hsi Wu ,  Der-Chyang Yeh ,  An-Jhih Su ,  Wei-Yu Chen

IPC: H01L21/48 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L23/498

Abstract: A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.

公开(公告)号：US20220199461A1

公开(公告)日：2022-06-23

申请号：US17205383

申请日：2021-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Wei-Yu Chen ,  Jiun Yi Wu ,  Chung-Shi Liu ,  Chien-Hsun Lee

IPC: H01L21/768 ,  H01L23/538 ,  H01L21/56 ,  H01L23/31

Abstract: A method includes attaching interconnect structures to a carrier substrate, wherein each interconnect structure includes a redistribution structure; a first encapsulant on the redistribution structure; and a via extending through the encapsulant to physically and electrically connect to the redistribution structure; depositing a second encapsulant on the interconnect structures, wherein adjacent interconnect structures are laterally separated by the second encapsulant; after depositing the second encapsulant, attaching a first core substrate to the redistribution structure of at least one interconnect structure, wherein the core substrate is electrically connected to the redistribution structure; and attaching semiconductor devices to the interconnect structures, wherein the semiconductor devices are electrically connected to the vias of the interconnect structures.

公开(公告)号：US11217570B2

公开(公告)日：2022-01-04

申请号：US16857161

申请日：2020-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  An-Jhih Su ,  Chi-Hsi Wu ,  Der-Chyang Yeh ,  Li-Hsien Huang ,  Po-Hao Tsai ,  Ming-Shih Yeh ,  Ta-Wei Liu

IPC: H01L25/10 ,  H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/538 ,  H01L21/768 ,  H01L25/065

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

公开(公告)号：US20210242119A1

公开(公告)日：2021-08-05

申请号：US16916046

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Lin Ho ,  Chin-Liang Chen ,  Jiun-Yi Wu ,  Chi-Yang Yu ,  Yu-Min Liang ,  Wei-Yu Chen

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a redistribution structure, a circuit substrate, and an insulating encapsulation. The redistribution structure includes a first under-bump metallization (UBM) pattern covered by a first dielectric layer, and the first UBM pattern includes a surface substantially leveled with a surface of the first dielectric layer. The circuit substrate is electrically coupled to the redistribution structure through a conductive joint disposed on the surface of the first UBM pattern. The insulating encapsulation is disposed on the redistribution structure to cover the circuit substrate.

公开(公告)号：US11049832B2

公开(公告)日：2021-06-29

申请号：US16876371

申请日：2020-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Jan Pei ,  Chih-Chiang Tsao ,  Wei-Yu Chen ,  Hsiu-Jen Lin ,  Ming-Da Cheng ,  Ching-Hua Hsieh ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L21/00 ,  H01L25/10 ,  H01L23/29 ,  H01L21/56 ,  H01L23/31 ,  H01L21/683 ,  H01L25/11

Abstract: A method for forming a package structure is provided. The method includes forming a protective layer to surround a semiconductor die and forming a conductive structure over the protective layer. The method also includes disposing a polymer-containing material over the protective layer to partially surround the conductive structure. The method further includes curing the polymer-containing material to form a warpage-control element.

公开(公告)号：US10734357B2

公开(公告)日：2020-08-04

申请号：US15801846

申请日：2017-11-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yu Chen ,  Li-Hsien Huang ,  An-Jhih Su ,  Hsien-Wei Chen

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/03 ,  H01L23/538 ,  H01L21/48

Abstract: A chip package structure is provided. The chip package structure includes a first chip, a second chip, and a third chip. The second chip is between the first chip and the third chip. The chip package structure includes a first molding layer surrounding the first chip. The chip package structure includes a second molding layer surrounding the second chip. The chip package structure includes an insulating layer between the first molding layer and the second molding layer and between the first chip and the second chip. A side wall of the first molding layer, a side wall of the second molding layer, and a side wall of the insulating layer are substantially coplanar. The chip package structure includes a third molding layer surrounding the third chip, the first molding layer, the second molding layer, and the insulating layer.

公开(公告)号：US09853008B2

公开(公告)日：2017-12-26

申请号：US15219357

申请日：2016-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Jen Tseng ,  Wei-Yu Chen ,  Ting-Wei Chiang ,  Li-Chun Tien

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/528 ,  H01L25/00 ,  H01L21/768 ,  H01L23/48 ,  H01L21/822 ,  H01L27/06 ,  H01L23/535 ,  H01L21/74 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L24/25 ,  H01L21/743 ,  H01L21/76838 ,  H01L21/8221 ,  H01L23/481 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/535 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: In some embodiments, the present disclosure relates to an integrated chip having an inter-tier interconnecting structure having horizontal components, which is arranged within a semiconductor substrate and configured to electrically couple a first device tier to a second device tier. The integrated chip has a first device tier with a first semiconductor substrate. A first inter-tier interconnecting structure is disposed inside the first semiconductor substrate. The first inter-tier interconnecting structure has a first segment extending in a first direction and a second segment protruding outward from a sidewall of the first segment in a second direction substantially perpendicular to the first direction. A second device tier is electrically coupled to the first device tier by the first inter-tier interconnecting structure.