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公开(公告)号：US20070080844A1
公开(公告)日：2007-04-12
申请号：US11543259
申请日：2006-10-05
IPC分类号： H03M1/12
CPC分类号： H03M1/1019 , H03M1/0636 , H03M1/0678 , H03M1/1225 , H03M1/20 , H03M1/50 , H03M1/502 , H03M1/60
摘要： In an analog-to-digital converter, a generating unit executes analog-to-digital conversion of a first input signal and a second input signal based on an analog-to-digital conversion characteristic curve to generate first digital data and second digital data respectively corresponding to the first input signal and the second input signal. The input signal has a first level, and the first level is the sum of an offset level and a level of a target analog signal for analog-to-digital conversion. The second input signal has a second level, and the second level is generated by subtracting the offset level from the level of the target analog signal. In the analog-to-digital converter, an obtaining unit obtains difference digital data between the first digital data and the second digital data to output the obtained difference digital data as digital data of the target analog signal.
摘要翻译： 在模拟 - 数字转换器中，生成单元基于模数转换特性曲线执行第一输入信号和第二输入信号的模数转换，分别产生第一数字数据和第二数字数据 对应于第一输入信号和第二输入信号。 输入信号具有第一电平，第一电平是用于模数转换的目标模拟信号的偏移电平和电平之和。 第二输入信号具有第二电平，并且通过从目标模拟信号的电平减去偏移电平来产生第二电平。 在模数转换器中，获取单元获得第一数字数据和第二数字数据之间的差数字数据，以将获得的差分数字数据作为目标模拟信号的数字数据输出。
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公开(公告)号：US20050047526A1
公开(公告)日：2005-03-03
申请号：US10926286
申请日：2004-08-26
IPC分类号： H03D1/22 , H04L27/00 , H04L27/227 , H04L27/38 , H04L27/06
CPC分类号： H04L27/00
摘要： In a synchronous detection method, an input signal is averaged over at least first and second phase ranges of a target carrier wave within each period thereof to obtain at least first and second moving average values of the input signal within the at least first and second phase ranges, respectively. The first phase range corresponds to a positively oscillating phase range of the target carrier wave, and the second phase range corresponds to a negatively oscillating phase range thereof. A difference between the first and second moving averages is calculated as a detection result of the target carrier wave.
摘要翻译： 在同步检测方法中，输入信号在其每个周期内的目标载波的至少第一和第二相位范围上进行平均，以在至少第一和第二阶段内获得输入信号的至少第一和第二移动平均值 范围。 第一相位范围对应于目标载波的正振荡相位范围，第二相位范围对应于其负振荡相位范围。 计算第一和第二移动平均值之间的差异作为目标载波的检测结果。
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43.发明授权Apparatus for detecting reciprocating motion of object and/or amplitude thereof 失效用于检测物体的往复运动和/或其振幅的装置公开(公告)号：US06700114B2
公开(公告)日：2004-03-02
申请号：US10150073
申请日：2002-05-20
IPC分类号： H01J314
CPC分类号： G02B26/105
摘要： A system working to detect a reciprocating motion of an object such as a scanner mirror of an optical scanner. The system is designed to compensate for an error which is concluded in an amplified sensor signal used to determine a reference position of the scanner mirror and which is sensitive to a change in environmental condition of use such as a change in ambient temperature. The system also works to monitor a change in amplitude of swing of the scanner mirror accurately to keep it constant.
摘要翻译： 一种用于检测物体（例如光学扫描仪的扫描镜）的往复运动的系统。 该系统被设计为补偿用于确定扫描器反射镜的参考位置的放大的传感器信号中所确定的误差，并且其对使用环境条件的变化（例如环境温度的变化）敏感。 该系统还可以准确地监测扫描仪镜的摆幅幅度变化，以保持其恒定。
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公开(公告)号：US6082196A
公开(公告)日：2000-07-04
申请号：US845895
申请日：1997-04-28
IPC分类号： G01D5/24 , G01P15/125 , G01P15/13 , G01P15/14
CPC分类号： G01P15/131 , G01P15/125
摘要： A physical quantity detecting is capable of easily adjusting sensitivity and an offset of a detected output without being increased in size. In a signal processor for driving a sensor element in which fixed electrodes are disposed on both sides of a movable electrode displaced in response to acceleration, a signal generator generates PWM signals PA and PB in which an invalid control period during which the fixed electrodes are both deenergized only during a period corresponding to data M3 stored in a memory, is, at a predetermined ratio, inserted into a valid control period during which the fixed electrodes are alternately energized and their energization ratio is controlled so that the movable electrode is placed in position. Since the sensitivity of the sensor element to the acceleration changes according to the length of the invalid control period which does not contribute to control of the position of the movable electrode, its sensitivity can be easily adjusted by simply changing the value set in the memory.
摘要翻译： 物理量检测能够容易地调节灵敏度和检测输出的偏移而不增大尺寸。 在用于驱动传感器元件的信号处理器中，其中固定电极设置在响应于加速度而移位的可移动电极的两侧，信号发生器产生PWM信号PA和PB，其中固定电极均为无效控制周期 仅在对应于存储在存储器中的数据M3的周期期间被断电，以预定比例插入到固定电极交替通电的有效控制周期中，并且控制其通电率，使得可动电极位于 。 由于传感器元件对加速度的灵敏度根据无效控制周期的长度而变化，这对于可移动电极的位置的控制无助于其灵敏度，因此可以通过简单地改变在存储器中设置的值来容易地调整灵敏度。
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公开(公告)号：US5936159A
公开(公告)日：1999-08-10
申请号：US755097
申请日：1996-11-25
申请人： Kazuhiko Kano , Yukihiro Takeuchi , Takamoto Watanabe , Kenichi Ao , Masakazu Kanosue , Hirofumi Uenoyama
发明人： Kazuhiko Kano , Yukihiro Takeuchi , Takamoto Watanabe , Kenichi Ao , Masakazu Kanosue , Hirofumi Uenoyama
CPC分类号： H01L21/28238 , G01P15/0802 , G01P15/124 , H01L29/51 , H01L29/84 , G01P2015/0814 , G01P2015/0828
摘要： A semiconductor sensor including a movable member beam structure having a reduced deflection characteristic. The sensor includes a movable beam structure film suspended from a semiconductor substrate, with a gap interposed between the beam structure film and the substrate. The beam structure film is composed of a plurality of film layers that are laminated in a direction of film thickness. Further, a stress relieving layer is interposed between respective films to reduce overall internal stress on the structure.
摘要翻译： 一种半导体传感器，包括具有减小的偏转特性的可动构件梁结构。 传感器包括从半导体衬底悬挂的可移动的光束结构膜，其间插入在光束结构膜和衬底之间。 束结构膜由沿膜厚方向层叠的多个膜层构成。 此外，应力消除层插入在各个膜之间以减小结构上的整体内部应力。
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公开(公告)号：US5534809A
公开(公告)日：1996-07-09
申请号：US212117
申请日：1994-03-14
申请人： Takamoto Watanabe , Seiki Aoyama
发明人： Takamoto Watanabe , Seiki Aoyama
CPC分类号： G01R25/00
摘要： A pulse phase difference encoding circuit includes a ring delay pulse generating circuit which is formed by a NAND circuit and inverters. Signal lines connecting the NAND circuit and the inverters have uniform load capacity to obtain even time resolutions. The NAND circuit is formed by component transistors one of which is larger in size to have the same delay time as the other inverters. A dedicated latch buffer for applying steeply changing drive pulse to a pulse selector is provided to prevent difference in the measurements. A specific value is outputted in the event of the overflow or underflow of the measurement time to obtain a constant digital output.
摘要翻译： 脉冲相位差编码电路包括由NAND电路和反相器形成的环形延迟脉冲发生电路。 连接NAND电路和逆变器的信号线具有均匀的负载能力，以获得均匀的时间分辨率。 NAND电路由分量晶体管形成，其中一个尺寸较大，具有与其它逆变器相同的延迟时间。 提供用于将急剧变化的驱动脉冲施加到脉冲选择器的专用锁存缓冲器，以防止测量的差异。 在测量时间的溢出或下溢的情况下，输出特定的值，以获得恒定的数字输出。
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47.发明授权Programmable delay line programmable delay circuit and digital controlled oscillator 失效可编程延迟线可编程延迟电路和数字控制振荡器
公开(公告)号：US5465076A
公开(公告)日：1995-11-07
申请号：US111488
申请日：1993-08-25
CPC分类号： H03K5/135 , H03K3/0315 , H03L7/0996 , H03L7/0997
摘要： A programmable delay line comprises a plurality of delay stages connected in series, each of the delay stages including: a basic path for passing an input signal; a delay path for passing the input signal with a predetermined delay time; and a selector for selecting either the basic path or the delay path to pass the input signal in accordance with digital data externally inputted, wherein differences in times for passing the input signal through the basic path and through the delay path in the plurality delay stages are UD.2.sup.n (n=0, 1, 2 . . . ), UD being unit delay time. A programmable delay apparatus comprises: an oscillator and counter, which determine a coarse delay time in accordance with the upper bit data of control data, and a programmable delay line, which determines a fine delay time according to the lower bit data of the control data after the finish of the coarse delay time to obtain a total delay time. The counter provides a wide range of available delay times. The oscillator of the programmable delay apparatus can be controlled by a control signal. Addition of a feedback circuit for supplying the delay signal from the delay line as the control signal to the oscillator of the programmable delay apparatus provides a digital controlled oscillator.
摘要翻译： 可编程延迟线包括串联连接的多个延迟级，每个延迟级包括：用于传递输入信号的基本路径; 用于以预定的延迟时间传递输入信号的延迟路径; 以及选择器，用于选择基本路径或延迟路径以根据外部输入的数字数据传递输入信号，其中通过基本路径的输入信号和通过多个延迟级中的延迟路径的时间差为 UD.2n（n = 0,1,2，...），UD为单位延迟时间。 一种可编程延迟装置包括：振荡器和计数器，其根据控制数据的高位数据确定粗延迟时间;以及可编程延迟线，其根据控制数据的较低位数据确定精细延迟时间 完成粗延时后获得总延迟时间。 该计数器提供广泛的可用延迟时间。 可编程延迟装置的振荡器可以通过控制信号来控制。 添加用于将来自延迟线的延迟信号作为控制信号提供给可编程延迟装置的振荡器的反馈电路提供数字控制振荡器。
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公开(公告)号：US5416444A
公开(公告)日：1995-05-16
申请号：US177682
申请日：1994-01-05
CPC分类号： H03K3/0315 , G01R25/08 , H03K5/131 , Y10S331/03
摘要： A ring oscillator for circulating pulse edges of two types therein includes an even number of inverting circuits connected in a ring. Each of the inverting circuits is operative to invert an input signal and output an inversion of the input signal. One of the inverting circuits is a first start inverting circuit which starts an operation of inverting an input signal in response to a first control signal applied from an external input. One of the inverting circuits except the first start inverting circuit and an inverting circuit immediately following the first start inverting circuit is a second start inverting circuit which starts an operation of inverting an input signal in response to a second control signal. A control signal inputting arrangement serves to input the second control signal to the second start inverting circuit during an interval from a first moment at which the first control signal is inputted into the first start inverting circuit and the first start inverting circuit starts the inverting operation to a second moment at which a pulse edge initially generated by the start of the inverting operation of the first start inverting circuit and travelling while being sequentially inverted by the inverting circuits enters the second start inverting circuit.
摘要翻译： 用于循环两种类型的脉冲边缘的环形振荡器包括以环形连接的偶数反相电路。 每个反相电路用于反转输入信号并输出输入信号的反相。 反相电路中的一个是第一启动反相电路，其响应于从外部输入施加的第一控制信号开始反相输入信号的操作。 除了第一启动反相电路和紧接在第一启动反相电路之后的反相电路之一的反相电路中的一个是响应于第二控制信号开始反相输入信号的操作的第二启动反相电路。 控制信号输入装置用于在从第一控制信号被输入到第一起动反向电路的第一时刻开始间隔期间将第二控制信号输入到第二启动反转电路，并且第一启动反相电路开始转换操作 第二时刻，由第一起动反转电路的反相操作开始初始产生的脉冲沿并且由反相电路顺序反转的第二时刻进入第二启动反相电路。
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公开(公告)号：US08436756B2
公开(公告)日：2013-05-07
申请号：US12955514
申请日：2010-11-29
申请人： Yukie Hashimoto , Takamoto Watanabe
发明人： Yukie Hashimoto , Takamoto Watanabe
IPC分类号： H03M1/06
CPC分类号： H03M1/0602 , H03M1/0836 , H03M1/14 , H03M1/502 , H03M1/60
摘要： An A/D conversion device includes an A/D conversion circuit that converts an inputted analog signal to digital data and outputs it, a digital signal correction unit that performs a correction process to the digital data and outputs a digital signal, and a phase compensation unit that performs phase compensation in accordance with a phase delay amount of the digital signal with respect to the analog signal generated in the A/D conversion circuit and the digital signal correction unit wherein the A/D conversion circuit comprises a pulse transit circuit, a transmit position detection structure, and a digital data creation structure, the delay characteristic of the digital data being identified from the inputted analog signal.
摘要翻译： A / D转换装置包括将输入的模拟信号转换为数字数据并输出的A / D转换电路，对数字数据执行校正处理并输出数字信号的数字信号校正单元，以及相位补偿 单元，其根据数字信号相对于在A / D转换电路中生成的模拟信号的相位延迟量和数字信号校正单元执行相位补偿，其中A / D转换电路包括脉冲传输电路， 发送位置检测结构和数字数据创建结构，根据输入的模拟信号识别数字数据的延迟特性。
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50.发明授权Method of placing delay units of pulse delay circuit on programmable logic device 有权在可编程逻辑器件上放置脉冲延迟电路的延迟单元的方法公开(公告)号：US08307320B2
公开(公告)日：2012-11-06
申请号：US12661156
申请日：2010-03-11
CPC分类号： H03K19/17736 , H03K19/17728
摘要： A method of placing delay units of a pulse delay circuit on a programmable logic device having logic cells in each of cell strings has a step of arranging each delay unit in one logic cell of the device such that the delay units are placed in respective specific cell strings aligned in a row direction and a step of serially connecting the delay units with one another as a straight delay line such that the delay units placed in the specific cell strings in the connecting order are aligned in the row direction. In the device, an inter-string transmission delay time on a line between two logic cells of different cell strings differs from an intra-string transmission delay time on a line between two logic cells of one cell string.
摘要翻译： 将脉冲延迟电路的延迟单元放置在具有每个单元串中的逻辑单元的可编程逻辑器件上的方法具有将每个延迟单元布置在器件的一个逻辑单元中的步骤，使得延迟单元放置在相应的特定单元中 在行方向排列的串和将延迟单元串联连接的直线延迟线的步骤，使得以连接顺序放置在特定单元串中的延迟单元在行方向上对齐。 在该装置中，不同单元串的两个逻辑单元之间的行上的串间传输延迟时间与一个单元串的两个逻辑单元之间的一行上的串内传输延迟时间不同。
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