公开(公告)号：US06495439B1

公开(公告)日：2002-12-17

申请号：US09819062

申请日：1999-06-22

Applicant: Jeffrey Peter Gambino ,  Son Van Nguyen ,  Reinhard Stengl

Inventor： Jeffrey Peter Gambino ,  Son Van Nguyen ,  Reinhard Stengl

IPC: H01L2128

CPC classification number: H01L21/02164 ,  H01L21/02129 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31612 ,  H01L21/76801 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10T428/24926 ,  H01L2924/00

Abstract: Significant amounts of pattern distortion were found to be the result of reflowing borophosphosilicate glass (BPSG) and silicon dioxide shrinkage during high temperature junction anneals. In order to remedy this problem, a method for suppressing the pattern distortion by subjecting the wafer coated with BPSG and with silicon dioxide layers to a high temperature anneal before patterning is disclosed. The high temperature anneal densifies the undoped silicon dioxide before patterning, so that shrinkage of the undoped silicon dioxide does not affect the patterning steps.

Abstract translation: 发现大量的图案变形是在高温结合退火期间回流硼磷硅酸盐玻璃（BPSG）和二氧化硅收缩的结果。 为了解决这个问题，公开了一种通过在涂布图案之前对涂覆有BPSG的晶片和二氧化硅层进行高温退火来抑制图案变形的方法。 在图案化之前，高温退火使未掺杂的二氧化硅致密化，使得未掺杂二氧化硅的收缩不影响图案化步骤。

公开(公告)号：US06215140B1

公开(公告)日：2001-04-10

申请号：US09398691

申请日：1999-09-20

Applicant: Hans Reisinger ,  Martin Franosch ,  Herbert Schäfer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

Inventor： Hans Reisinger ,  Martin Franosch ,  Herbert Schäfer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

IPC: H01L2972

CPC classification number: H01L21/8229 ,  H01L27/1021

Abstract: A memory cell configuration in a semiconductor substrate is proposed, in which the semiconductor substrate is of the first conductivity type. Trenches which run parallel to one another are incorporated in the semiconductor substrate, and first address lines run along the side walls of the trenches. Second address lines are formed on the semiconductor substrate, transversely with respect to the trenches. Semiconductor substrate regions, in which a diode and a dielectric whose conductivity can be changed are arranged, are located between the first address lines and the second address lines. A suitable current pulse can be used to produce a breakdown in the dielectric, with information thus being stored in the dielectric.

Abstract translation: 提出半导体衬底中的存储单元结构，其中半导体衬底是第一导电类型。 相互平行延伸的沟槽并入半导体衬底中，并且第一地址线沿着沟槽的侧壁延伸。 第二地址线在半导体衬底上相对于沟槽横向地形成。 布置有可以改变导电性的二极管和电介质的半导体衬底区域位于第一地址线和第二地址线之间。 可以使用合适的电流脉冲来产生电介质中的击穿，由此将信息存储在电介质中。

公开(公告)号：US06197666B1

公开(公告)日：2001-03-06

申请号：US09390496

申请日：1999-09-03

Applicant: Herbert Schafer ,  Martin Franosch ,  Reinhard Stengl ,  Hans Reisinger ,  Matthias Ilg

Inventor： Herbert Schafer ,  Martin Franosch ,  Reinhard Stengl ,  Hans Reisinger ,  Matthias Ilg

IPC: H01L2120

CPC classification number: H01L27/10873 ,  C23C16/24 ,  C23C16/56 ,  H01L21/28035 ,  H01L21/32055 ,  H01L21/76877

Abstract: A method for the fabrication of a doped silicon layer, includes carrying out deposition by using a process gas containing SiH4, Si2H6 and a doping gas. The doped silicon layer which is thus produced can be used both as a gate electrode of an MOS transistor and as a conductive connection. At a thickness between 50 and 200 nm it has a resistivity less than or equal to 0.5 m&OHgr;cm.

Abstract translation: 一种用于制造掺杂硅层的方法，包括通过使用含有SiH 4，Si 2 H 6和掺杂气体的工艺气体进行沉积。 由此制造的掺杂硅层既可以用作MOS晶体管的栅电极，也可以用作导电连接。 在50至200nm的厚度之间，其电阻率小于或等于0.5mOMEGAcm。

公开(公告)号：US6133126A

公开(公告)日：2000-10-17

申请号：US398688

申请日：1999-09-20

Applicant: Hans Reisinger ,  Martin Franosch ,  Herbert Schafer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

Inventor： Hans Reisinger ,  Martin Franosch ,  Herbert Schafer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

IPC: H01L21/225 ,  H01L21/768 ,  H01L21/8239 ,  H01L27/105 ,  H01L21/22

CPC classification number: H01L21/76888 ,  H01L21/2256 ,  H01L27/105 ,  H01L27/1052

Abstract: A method for fabricating a dopant region is disclosed. The dopant region is formed by providing a semiconductor substrate that has a surface. An electrically insulating intermediate layer is applied to the surface. A doped semiconductor layer is then applied to the electrically insulating intermediate layer, the semiconductor layer being of a first conductivity type and contains a dopant of the first conductivity type. A temperature treatment of the semiconductor substrate at a predefined diffusion temperature is performed, so that the dopant diffuses partially out of the semiconductor layer through the intermediate layer into the semiconductor substrate and forms there a dopant region of the first conductivity type. The electrical conductivity of the intermediate layer is modified, so that an electrical contact between the semiconductor substrate and the semiconductor layer is produced through the intermediate layer.

Abstract translation: 公开了一种制造掺杂剂区域的方法。 通过提供具有表面的半导体衬底形成掺杂剂区域。 将电绝缘的中间层施加到表面。 然后将掺杂半导体层施加到电绝缘中间层，所述半导体层是第一导电类型并且包含第一导电类型的掺杂剂。 执行预定扩散温度下的半导体衬底的温度处理，使得掺杂剂从半导体层中部分扩散通过中间层进入半导体衬底，并在其上形成第一导电类型的掺杂区域。 改变中间层的导电性，从而通过中间层产生半导体衬底和半导体层之间的电接触。

公开(公告)号：US6037209A

公开(公告)日：2000-03-14

申请号：US254696

申请日：1999-03-15

Applicant: Wolfgang Rosner ,  Lothar Risch ,  Franz Hofmann ,  Reinhard Stengl

Inventor： Wolfgang Rosner ,  Lothar Risch ,  Franz Hofmann ,  Reinhard Stengl

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10876 ,  H01L27/10823

Abstract: The DRAM cell arrangement comprises, per memory cell, a vertical MOS transistor whose first source/drain region is connected to a storage node of a storage capacitor, whose channel region (3) is annularly enclosed by a gate electrode (13) and whose second source/drain region is connected to a buried bit line. The DRAM cell arrangement is produced using only two masks, with the aid of a spacer technique, with a memory cell area of 2F.sup.2, where F is the minimum structure size which can be produced using the respective technology.

Abstract translation: PCT No.PCT / DE97 / 01580 Sec。 371 1999年3月15日 102（e）1999年3月15日PCT 1997年7月28日PCT公布。 出版物WO98 / 11604 日期1998年3月19日DRAM单元布置包括每个存储单元的垂直MOS晶体管，其第一源极/漏极区域连接到存储电容器的存储节点，其沟道区域（3）被栅电极环形封闭 13），并且其第二源极/漏极区域连接到掩埋位线。 借助于间隔器技术，仅使用两个掩模来制造DRAM单元布置，存储单元面积为2F2，其中F是可以使用各自技术产生的最小结构尺寸。

公开(公告)号：US5844266A

公开(公告)日：1998-12-01

申请号：US879871

申请日：1997-06-20

Applicant: Reinhard Stengl ,  Erwin Hammerl ,  Herbert L. Ho ,  Jack A. Mandelman ,  Radhika Srinivasan ,  Alvin P. Short

Inventor： Reinhard Stengl ,  Erwin Hammerl ,  Herbert L. Ho ,  Jack A. Mandelman ,  Radhika Srinivasan ,  Alvin P. Short

IPC: H01L27/00 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

CPC classification number: H01L27/10861 ,  H01L27/10832

Abstract: In a method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell, the electrical connection is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.

Abstract translation: 在用于在DRAM单元中的沟槽存储电容器和存取晶体管之间进行电连接的方法中，通过选择性地控制存在于沟槽中的N型或P型掺杂剂的扩散，通过单晶 半导体材料，其通过从沟槽侧壁外延（epi）生长。 该外延生长的单晶层作为在常规DRAM的处理中可能发生的过量掺杂剂扩散扩散的障碍。

公开(公告)号：US5360759A

公开(公告)日：1994-11-01

申请号：US123605

申请日：1993-09-17

Applicant: Reinhard Stengl ,  Wolfgang Hoenlein ,  Volker Lehmann ,  Andreas Spitzer

Inventor： Reinhard Stengl ,  Wolfgang Hoenlein ,  Volker Lehmann ,  Andreas Spitzer

IPC: H01L21/28 ,  H01L21/306 ,  H01L31/11 ,  H01L33/34 ,  H01L21/283 ,  H01L21/265

CPC classification number: H01L33/346 ,  H01L21/306 ,  H01L31/1105 ,  Y10S438/96

Abstract: For manufacturing a component with porous silicon, two highly doped regions with a lightly doped region arranged between them are formed in a silicon wafer. The dopant concentrations are thereby set such that porous silicon arises in the lightly doped region in a subsequent anodic etching. Light-emitting diodes or light-controlled bipolar transistors can be manufactured in this way.

Abstract translation: 为了制造具有多孔硅的部件，在硅晶片中形成具有布置在它们之间的轻掺杂区域的两个高掺杂区域。 因此，掺杂剂浓度被设定为使得随后的阳极蚀刻在轻掺杂区域中产生多孔硅。 可以以这种方式制造发光二极管或光控双极晶体管。

公开(公告)号：US4672738A

公开(公告)日：1987-06-16

申请号：US776161

申请日：1985-09-13

Applicant: Reinhard Stengl ,  Ulrich Goesele ,  Christine Fellinger

Inventor： Reinhard Stengl ,  Ulrich Goesele ,  Christine Fellinger

IPC: H01L21/033 ,  H01L21/22 ,  H01L21/265 ,  H01L21/266 ,  H01L29/06 ,  H01L29/74

CPC classification number: H01L21/0334 ,  H01L21/266 ,  H01L29/0615 ,  H01L29/0688 ,  Y10S148/01 ,  Y10S438/965

Abstract: A method for the manufacture of a pn junction having a high breakdown voltage at the boundary surface of a semiconductor body, utilizing a mask which has a relatively large opening for introducing a dopant therethrough into the semiconductor body, the mask having a marginal edge which extends laterally beyond the edge of the relatively large opening. In the marginal edge, the mask is provided with smaller, auxiliary openings, the openings being sized and spaced such that lesser amounts of dopant pass through the opening as the distance of the auxiliary openings from the edge of the relatively larger opening increases. Upon introducing the dopant into the semiconductor body through the mask, there is generated a doping profile which gradually approaches the boundary surface with increasing distance from the edge of the relatively large opening.

Abstract translation: 一种用于制造在半导体本体的边界表面具有高击穿电压的pn结的方法，利用具有相对较大的开口的掩模，用于将掺杂剂引入到半导体本体中，所述掩模具有延伸的边缘 横向超过相对较大开口的边缘。 在边缘处，掩模设置有较小的辅助开口，开口的尺寸和间隔使得当辅助开口距相对较大开口的边缘的距离增加时，较少量的掺杂剂通过开口。 当通过掩模将掺杂剂引入半导体本体时，产生掺杂分布，其随着距离相对大的开口的边缘的距离增加而逐渐接近边界表面。

公开(公告)号：US20110042046A1

公开(公告)日：2011-02-24

申请号：US12940713

申请日：2010-11-05

Applicant: Volker Lehmann ,  Reinhard Stengl ,  Herbert Schäfer

Inventor： Volker Lehmann ,  Reinhard Stengl ,  Herbert Schäfer

IPC: F28D15/04 ,  H01L21/306

CPC classification number: H01L23/473 ,  H01L21/30604 ,  H01L21/3063 ,  H01L23/427 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

Abstract: An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is provided. At least one integrated electronic component is arranged at a main area of a substrate. The component is arranged in the substrate or is isolated from the substrate by an electrically insulating region. Main channels are formed in the substrate and arranged along the main area. Each main channel is completely surrounded by the substrate transversely with respect to a longitudinal axis. Transverse channels are arranged transversely with respect to the main channels. Each transverse channel opens into at least one main channel. More than about ten transverse channels open into a main channel.

Abstract translation: 提供一种集成电路装置及其制造方法。 至少一个集成电子部件布置在基板的主要区域。 该部件布置在基板中，或者通过电绝缘区域与基板隔离。 主通道形成在基板上并且沿着主区域布置。 每个主通道相对于纵向轴线横向地完全被基底包围。 横向通道相对于主通道横向布置。 每个横向通道打开至少一个主通道。 超过十个横向通道进入主通道。

公开(公告)号：US06710388B2

公开(公告)日：2004-03-23

申请号：US09801209

申请日：2001-03-07

Applicant: Thomas Peter Haneder ,  Hans Reisinger ,  Reinhard Stengl ,  Harald Bachhofer ,  Hermann Wendt ,  Wolfgang Hönlein

Inventor： Thomas Peter Haneder ,  Hans Reisinger ,  Reinhard Stengl ,  Harald Bachhofer ,  Hermann Wendt ,  Wolfgang Hönlein

IPC: H01L27108

CPC classification number: G11C11/22 ,  H01L29/78391

Abstract: A ferroelectric transistor suitable as a memory element has a first gate intermediate layer and a first gate electrode disposed on the surface of a semiconductor substrate and disposed between source/drain regions. The first gate intermediate layer contains at least one ferroelectric layer. In addition to the first gate intermediate layer, a second gate intermediate layer and a second gate electrode are configured between the source/drain regions. The second gate intermediate layer contains a dielectric layer. The first gate electrode and the second gate electrode are connected to each other via a diode structure.

Abstract translation: 适合作为存储元件的铁电晶体管具有设置在半导体衬底的表面上并设置在源极/漏极区之间的第一栅极中间层和第一栅电极。 第一栅极中间层包含至少一个铁电层。 除了第一栅极中间层之外，在源极/漏极区域之间配置第二栅极中间层和第二栅极电极。 第二栅极中间层包含电介质层。 第一栅电极和第二栅极通过二极管结构彼此连接。