公开(公告)号：US20110309365A1

公开(公告)日：2011-12-22

申请号：US13219571

申请日：2011-08-26

Applicant: Ping Mei ,  Hao Luo ,  Albert Hua Jeans ,  Angeles Marcia Almanza-Workman ,  Robert A. Garcia ,  Warren Jackson ,  Carl P. Taussig ,  Craig M. Perlov

Inventor： Ping Mei ,  Hao Luo ,  Albert Hua Jeans ,  Angeles Marcia Almanza-Workman ,  Robert A. Garcia ,  Warren Jackson ,  Carl P. Taussig ,  Craig M. Perlov

IPC: H01L33/08

CPC classification number: H01L27/1288 ,  H01L27/1214 ,  Y10S438/942

Abstract: A fabrication process for a device such as a backplane for a flat panel display includes depositing thin film layers on a substrate, forming a 3D template overlying the thin film layers, and etching the 3D template and the thin film layers to form gate lines and transistors from the thin film layers. An insulating or passivation layer can then be deposited on the gate lines and the transistors, so that column or data lines can be formed on the insulating layer.

Abstract translation: 用于平板显示器的背板的装置的制造方法包括在衬底上沉积薄膜层，形成覆盖薄膜层的3D模板，以及蚀刻3D模板和薄膜层以形成栅线和晶体管 从薄膜层。 然后可以在栅极线和晶体管上沉积绝缘或钝化层，使得可以在绝缘层上形成列或数据线。

公开(公告)号：US20090142560A1

公开(公告)日：2009-06-04

申请号：US11948867

申请日：2007-11-30

Applicant: Warren Jackson ,  Carl P. Taussig ,  Ping Mei ,  Albert Jeans ,  Han-Jun Kim

Inventor： Warren Jackson ,  Carl P. Taussig ,  Ping Mei ,  Albert Jeans ,  Han-Jun Kim

IPC: B32B7/02

CPC classification number: B82Y10/00 ,  B32B7/02 ,  B82Y40/00 ,  G03F7/0002 ,  Y10T428/24942

Abstract: This invention provides a thin film device with minimized spatial variation of local mean height. More specifically, the thin film device has a substrate and at least one first structure having a first spatially varying weighted local mean height determined by a layer weighting function. The first structure has a first maximum height, a first minimum height and a first variation for a given averaging area. A compensation structure is also provided upon the substrate, the compensation structure having a second spatially varying weighted local mean height determined by the layer weighting function. The compensation structure also has a second maximum height, a second minimum height and a second variation for the given averaging area. The first structure and compensation structure combine to provide a combined structure upon the substrate with minimized spatial variation of a combined weighted local mean.

Abstract translation: 本发明提供一种具有最小的局部平均高度的空间变化的薄膜装置。 更具体地，薄膜器件具有衬底和至少一个具有由层加权函数确定的具有第一空间变化的加权局部平均高度的第一结构。 第一结构具有给定平均区域的第一最大高度，第一最小高度和第一变化。 还在衬底上提供补偿结构，补偿结构具有由层加权函数确定的第二空间变化的加权局部平均高度。 补偿结构还具有给定平均区域的第二最大高度，第二最小高度和第二变化。 第一结构和补偿结构结合在一起，在基底上提供组合结构，使组合加权局部平均值具有最小的空间变化。

公开(公告)号：US07251783B2

公开(公告)日：2007-07-31

申请号：US10286028

申请日：2002-11-01

Applicant: Warren Jackson ,  Ping Mei

Inventor： Warren Jackson ,  Ping Mei

IPC: G03B15/00

CPC classification number: G06F1/1601 ,  G02F1/136286 ,  G02F1/1368 ,  G06F3/1423

Abstract: A large area display workstation provides a liquid crystal display, configured to produce an image. The electrical components of the liquid crystal display are disposed on a substrate through a large area fabrication technique. The workstation has a first, high-resolution video display, and the large area display is a second, lower-resolution file identification display. The computer displays a user-selected file in a high-resolution format on the high-resolution video display for manipulation, and displays a plurality of file indicators in a low-resolution format on the large area display.

Abstract translation: 大面积显示工作站提供液晶显示器，用于产生图像。 液晶显示器的电气部件通过大面积制造技术设置在基板上。 工作站具有第一个高分辨率视频显示，大面积显示是第二个较低分辨率的文件识别显示。 计算机在高分辨率视频显示器上以高分辨率格式显示用户选择的文件进行操作，并在大面积显示器上以低分辨率格式显示多个文件指示符。

公开(公告)号：US20060028895A1

公开(公告)日：2006-02-09

申请号：US10914255

申请日：2004-08-09

Applicant: Carl Taussig ,  Warren Jackson ,  Craig Perlov ,  Frank Jeffrey

Inventor： Carl Taussig ,  Warren Jackson ,  Craig Perlov ,  Frank Jeffrey

IPC: G11C17/18 ,  G11C11/36

CPC classification number: H01L23/5252 ,  G11C13/02 ,  G11C17/16 ,  G11C17/18 ,  G11C2213/72 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An silver island anti-fuse including a first electrical conductor, an electrically resistive material in contact with the first conductor and at least one silver island disposed opposite the first electrical conductor and upon the electrically resistive material. A second electrical conductor disposed over the silver island intimately couples the silver island to the electrically resistive material. When a critical potential is applied across the anti-fuse, a metallic filament precipitates from the silver island through the electrically resistive material layer, establishing a short and thus switching the silver island anti-fuse from a high resistance to a low resistance. A method of making the silver island anti-fuse and a memory device incorporating the silver island anti-fuse are further provided.

Abstract translation: 一种银岛反熔丝，包括第一电导体，与第一导体接触的电阻材料和与第一电导体相对设置的至少一个银岛和电阻材料。 布置在银岛上的第二电导体将银岛紧密地耦合到电阻材料上。 当跨抗反熔丝施加临界电位时，金属细丝通过电阻材料层从银岛沉淀出来，建立短路，从而将银岛抗熔丝从高电阻切换到低电阻。 还提供了制造银岛反熔丝的方法和结合有银岛反熔丝的存储装置。

公开(公告)号：US20050271869A1

公开(公告)日：2005-12-08

申请号：US10863129

申请日：2004-06-07

Applicant: Warren Jackson

Inventor： Warren Jackson

IPC: B32B27/04 ,  B32B27/08 ,  B32B27/12

CPC classification number: B32B27/12 ,  B32B7/12 ,  B32B2260/021 ,  B32B2307/514 ,  B32B2307/732 ,  C09J7/00 ,  C09J2201/626 ,  D04H1/58 ,  D04H11/00 ,  Y10T428/24994 ,  Y10T428/31507 ,  Y10T428/31721 ,  Y10T428/31725 ,  Y10T428/31786

Abstract: Embodiments of the present invention include hierarchically-dimensioned, microfiber-based dry adhesive materials featuring dense arrays of microfibers with free tips terminating in numerous microfibrils. In certain embodiments, more than two levels of microfiber-dimension hierarchy may be employed, each dimension involving smaller microfibrils emanating from the tips of the microfibers or microfibrils of the next highest dimensional level. Various additional embodiments of the present invention are directed to methods for preparing hierarchically-dimensioned, microfiber-based dry adhesive materials. These methods include single-pass or multi-pass imprint-lithography, pattern masking and etching, and imprinting fiber-embedded substrates followed by etching.

公开(公告)号：US06967149B2

公开(公告)日：2005-11-22

申请号：US10718137

申请日：2003-11-20

Applicant: Neal W. Meyer ,  Andrew L. Van Brocklin ,  Peter Fricke ,  Warren Jackson ,  Kenneth James Eldredge

Inventor： Neal W. Meyer ,  Andrew L. Van Brocklin ,  Peter Fricke ,  Warren Jackson ,  Kenneth James Eldredge

IPC: H01L27/10 ,  H01L21/02 ,  H01L21/20 ,  H01L21/762 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/12 ,  H01L21/30

CPC classification number: H01L21/76254 ,  H01L21/2007

Abstract: Apparatus and method for making a multi-layered storage structure includes forming a device layer on a single-crystal wafer, cleaving the device layer from the wafer, repeating the forming and cleaving to provide a plurality of cleaved device layers, and bonding the cleaved device layers together to form the multi-layered storage structure.

Abstract translation: 用于制造多层存储结构的装置和方法包括在单晶晶片上形成器件层，从晶片切割器件层，重复形成和切割以提供多个切割的器件层，以及将切割的器件 层叠在一起形成多层存储结构。

公开(公告)号：US20050135146A1

公开(公告)日：2005-06-23

申请号：US10739350

申请日：2003-12-19

Applicant: Carl Taussig ,  Warren Jackson ,  Hao Luo

Inventor： Carl Taussig ,  Warren Jackson ,  Hao Luo

IPC: G11C17/14 ,  G11C5/02 ,  G11C7/00 ,  G11C8/00 ,  G11C8/10 ,  G11C11/00 ,  G11C16/02 ,  G11C17/16 ,  G11C17/18 ,  H01L27/10

CPC classification number: G11C17/16 ,  G11C5/025 ,  G11C8/10 ,  G11C13/0023 ,  G11C17/165 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77

Abstract: An addressing circuit is operable to address one or more memory elements in a cross-point memory array. The addressing circuit includes first and second sets of address lines for addressing the cross-point memory array. The address circuit also includes pull-up and pull-down circuit elements. Both the pull-up and pull-down circuit elements and the address lines include cross-point resistive elements.

公开(公告)号：US20050093092A1

公开(公告)日：2005-05-05

申请号：US10695710

申请日：2003-10-29

Applicant: Lung Tran ,  Andrew Van Brocklin ,  Warren Jackson ,  Janice Nickel

Inventor： Lung Tran ,  Andrew Van Brocklin ,  Warren Jackson ,  Janice Nickel

IPC: G11C11/16 ,  G11C17/16 ,  G11C17/18 ,  H01L27/10 ,  H01L29/00

CPC classification number: H01L27/101 ,  G11C11/16 ,  G11C17/16

Abstract: A resistive cross point array memory device comprising a plurality of word lines extending in a row direction, a plurality of bit lines extending in a column direction such that a plurality of cross points is formed at intersections between the word and bit lines, and at least one memory element formed in at least one of the cross points. The memory element comprises a first tunnel junction having a bottom conductor, a top conductor, a barrier layer adjacent the bottom conductor, and wherein the bottom conductor comprises a non-uniform upper surface.

Abstract translation: 一种电阻式交叉点阵列存储器件，包括沿行方向延伸的多条字线，沿列方向延伸的多条位线，使得多个交叉点形成在字和位线之间的交叉处，至少 一个存储元件形成在至少一个交叉点上。 存储元件包括具有底部导体，顶部导体，邻近底部导体的阻挡层的第一隧道结，并且其中底部导体包括不均匀的上表面。

公开(公告)号：US20050006640A1

公开(公告)日：2005-01-13

申请号：US10608791

申请日：2003-06-26

Applicant: Warren Jackson ,  Sean Zhang ,  Craig Perlov

Inventor： Warren Jackson ,  Sean Zhang ,  Craig Perlov

IPC: G11C13/02 ,  H01L27/28 ,  H01L51/00 ,  H01L51/30 ,  H01L47/00

CPC classification number: G11C13/0016 ,  B82Y10/00 ,  G11C13/0014 ,  H01L27/28 ,  H01L51/0034 ,  H01L51/0035 ,  H01L51/0036 ,  H01L51/0037 ,  H01L51/0038 ,  H01L51/0041

Abstract: Fuse-type and antifuse-type semiconducting-organic-polymer-film-based memory elements for use in memory devices are disclosed. Various embodiments of the present invention employ a number of different techniques to alter the electrical conductance or, equivalently, the resistance, of organic-polymer-film memory elements in order to produce detectable memory-state changes in the memory elements. The techniques involve altering the electronic properties of the organic polymers by application of heat or electric fields, often in combination with additional chemical compounds, to either increase or decrease the resistance of the organic polymers.

Abstract translation: 公开了用于存储器件的保险丝型和反熔丝型半导体 - 有机聚合物膜基存储元件。 本发明的各种实施例使用多种不同的技术来改变有机 - 聚合物膜存储元件的电导率或等效的电阻，以便产生存储元件中的可检测的存储状态变化。 这些技术涉及通过施加热或电场（通常与其它化合物组合）来改变有机聚合物的电子性质来提高或降低有机聚合物的电阻。

公开(公告)号：US08729518B2

公开(公告)日：2014-05-20

申请号：US13281186

申请日：2011-10-25

Applicant: Matthew D. Pickett ,  R. Stanley Williams ,  Gilberto M. Ribeiro ,  Warren Jackson

Inventor： Matthew D. Pickett ,  R. Stanley Williams ,  Gilberto M. Ribeiro ,  Warren Jackson

IPC: H01L47/00

CPC classification number: H01L47/00 ,  H01L27/26 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  Y10T428/197 ,  Y10T428/24802 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: A multilayer structure is disclosed that includes a conductive layer, a layer of a negative differential resistance (NDR) material disposed above the conductive layer, a layer M2 disposed above the NDR material, a second layer of NDR material disposed above layer M2, and a conductive layer disposed above the second NDR layer. Layer M2 can include a conductive material interspersed with regions of a dielectric material or a layer of the dielectric material and regions of the conductive material disposed above and below the dielectric material.

Abstract translation: 公开了一种多层结构，其包括导电层，设置在导电层上方的负差动电阻（NDR）材料层，设置在NDR材料上方的层M2，设置在层M2上方的NDR材料的第二层，以及 导电层设置在第二NDR层之上。 层M2可以包括散布有电介质材料的区域或电介质材料层的导电材料和设置在电介质材料上方和下方的导电材料的区域。