公开(公告)号：US06498063B1

公开(公告)日：2002-12-24

申请号：US09975879

申请日：2001-10-12

申请人： Er-Xuan Ping

发明人： Er-Xuan Ping

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L21/3185 ,  H01L27/10817 ,  H01L28/75 ,  H01L28/84 ,  H01L28/90 ,  H01L28/91

摘要： A method of providing even nucleation between silicon and oxide surfaces for growing uniformly thin silicon nitride layers used in semiconductor devices. First, a nonconductive nitride-nucleation enhancing monolayer is formed over a semiconductor assembly having both nitridation receptive and resistive materials. For purposes of the present invention, a nitride-nucleation enhancing monolayer is a material that will readily accept the bonding of nitrogen atoms to the material itself. Next, a silicon nitride layer is formed over the nonconductive nitride-nucleation enhancing monolayer. The nonconductive nitride-nucleation enhancing monolayer provides even nucleation over both the nitridation receptive material and the nitridation resistive material for silicon nitride, thereby allowing for the growth of a uniformly thin nitride layer.

摘要翻译： 在硅和氧化物表面之间提供均匀成核的方法，用于生长半导体器件中使用的均匀薄的氮化硅层。 首先，在具有氮化接受和电阻材料的半导体组件上形成非导电氮化物成核增强单层。 为了本发明的目的，氮化物成核增强单层是容易接受氮原子结合到材料本身的材料。 接下来，在非导电氮化物成核增强单层上形成氮化硅层。 非导电氮化物成核增强单层在氮化接触材料和用于氮化硅的氮化电阻材料两者上均匀成核，从而允许生长均匀的氮化物薄层。

公开(公告)号：US06351005B1

公开(公告)日：2002-02-26

申请号：US09579821

申请日：2000-05-25

申请人： Husam N. Al-Shareef ,  Er-Xuan Ping

发明人： Husam N. Al-Shareef ,  Er-Xuan Ping

IPC分类号： H01L27108

CPC分类号： H01L28/55 ,  H01L27/10852 ,  H01L28/82 ,  H01L28/91

摘要： An integrated capacitor is provided, incorporating a high dielectric constant material. In a disclosed method, a high k capacitor dielectric is formed in the shape of a container above a protective layer. After the dielectric is formed, inner and outer electrodes are formed, representing storage and reference electrodes of a memory cell. Contact is separately made through the protective layer from a storage electrode layer, which lines the inner surface of the dielectric, to an underlying polysilicon plug. The contact can be a thin layer lining the interior of the storage electrode layer, or can completely fill the container capacitor. In the latter instance, the contact can form part of the storage electrode and contribute to capacitance of the cell. Volatile dielectric materials can thus be formed prior to the electrodes, avoiding oxidation of the electrodes and underlying polysilicon plug, while also minimizing oxygen depletion through diffusion from the high dielectric constant material.

摘要翻译： 提供了一种集成电容器，其包括高介电常数材料。 在公开的方法中，高k电容器电介质形成为保护层上方的容器形状。 在形成电介质之后，形成表示存储单元的存储和参考电极的内部和外部电极。 接触件通过保护层从存储电极层分别制成，该电极层将电介质的内表面排列到下面的多晶硅插塞。 接触可以是在存储电极层的内部衬里的薄层，或者可以完全填充容器电容器。 在后一种情况下，接触可以形成存储电极的一部分并有助于电池的电容。 因此，可以在电极之前形成挥发性介电材料，避免电极和下面的多晶硅插塞的氧化，同时还通过从高介电常数材料的扩散减少氧耗尽。

公开(公告)号：US06313026B1

公开(公告)日：2001-11-06

申请号：US09546068

申请日：2000-04-10

申请人： Yin Huang ,  Er-Xuan Ping

发明人： Yin Huang ,  Er-Xuan Ping

IPC分类号： H01L214763

CPC分类号： H01L21/76838 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for producing reliable contacts in microelectronic devices and contacts produced thereby are provided. In one embodiment of the invention, a first conductive layer is formed over a first dielectric layer. The first conductive layer contains a pattern etched therein. A second dielectric layer is deposited over the first conductive layer and a via is etched therein over the pattern, thus exposing a portion of the pattern and the first conductive layer. The structure is then further etched to remove a portion of the first dielectric layer using the exposed portions of the first conductive layer as a mask. The structure is then subject to an isotropic etch to create undercuts in the first dielectric layer underneath the exposed portions of the first conductive layer. A conductive material can then be deposited into the via to fill the undercut, thus contacting the first conductive material on the exposed top, sides, and underside of the layer to produce a highly reliable contact. This technique is also adapted to create vias that are used to connect three or more conductive layers.

摘要翻译： 提供了一种用于在微电子器件中产生可靠的触点的方法和由此产生的触点。 在本发明的一个实施例中，在第一电介质层上形成第一导电层。 第一导电层包含蚀刻在其中的图案。 在第一导电层上沉积第二电介质层，并且在图案上蚀刻通孔，从而暴露图案的一部分和第一导电层。 然后使用第一导电层的暴露部分作为掩模，进一步蚀刻该结构以去除第一介电层的一部分。 然后将该结构进行各向同性蚀刻，以在第一导电层的暴露部分下面的第一介电层中产生底切。 然后可以将导电材料沉积到通孔中以填充底切，从而使第一导电材料接触在该层的暴露的顶部，侧面和下侧，以产生高度可靠的接触。 该技术还适于产生用于连接三个或更多个导电层的通孔。

公开(公告)号：US6083849A

公开(公告)日：2000-07-04

申请号：US18228

申请日：1998-02-03

申请人： Er-Xuan Ping ,  Li Li

发明人： Er-Xuan Ping ,  Li Li

IPC分类号： C09K13/06 ,  H01L21/02 ,  H01L21/306 ,  H01L21/302

CPC分类号： H01L21/02049 ,  C09K13/06 ,  H01L21/02063 ,  H01L21/02068 ,  H01L28/84

摘要： In one aspect, the invention encompasses a semiconductor processing method comprising contacting a surface with a liquid solution comprising at least one fluorine-containing species and a temperature of at least about 40.degree. C. In another aspect, the invention encompasses a method of passivating a silicon-comprising layer comprising contacting the layer with a liquid solution comprising hydrogen fluoride and a temperature of at least about 40.degree. C. In yet another aspect, the invention encompasses a method of forming hemispherical grain polysilicon comprising: a) forming a layer comprising substantially amorphous silicon over a substrate; b) contacting the layer comprising substantially amorphous silicon with a liquid solution comprising fluorine-containing species and a temperature of at least about 40.degree. C.; c) seeding the layer comprising substantially amorphous silicon; and d) annealing the seeded layer to convert at least a portion of the seeded layer to hemispherical grain polysilicon.

摘要翻译： 一方面，本发明包括一种半导体处理方法，其包括将表面与包含至少一种含氟物质的液体溶液和至少约40℃的温度接触。另一方面，本发明包括一种钝化方法 含硅层包括使该层与包含氟化氢的液体溶液接触并且至少约40℃的温度。在另一方面，本发明包括形成半球形晶粒多晶硅的方法，包括：a）形成包括基本上 非晶硅; b）使包含基本上非晶硅的层与包含含氟物质的液体溶液和至少约40℃的温度接触; c）将包含基本上非晶硅的层接种; 以及d）退火所述接种层以将所述接种层的至少一部分转化为半球形晶粒多晶硅。

公开(公告)号：US6015997A

公开(公告)日：2000-01-18

申请号：US803174

申请日：1997-02-19

申请人： Yongjun Hu ,  Pai-Hung Pan ,  Er-Xuan Ping ,  Randhir P.S. Thakur ,  Scott DeBoer

发明人： Yongjun Hu ,  Pai-Hung Pan ,  Er-Xuan Ping ,  Randhir P.S. Thakur ,  Scott DeBoer

IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L29/76 ,  H01L29/74 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L21/28044 ,  H01L21/28052 ,  H01L29/4941

摘要： Methods and apparatus for forming word line stacks comprise one, or a combination of the following: a silicon diffusion barrier layer, doped with oxygen or nitrogen, coupled between a bottom silicon layer and a conductor layer; an amorphous silicon diffusion barrier coupled between a polysilicon layer and a conductor layer; a thin nitride layer coupled between a bottom silicon layer and a titanium silicide conductor layer, and a bottom silicon layer coupled to a conductor layer, which comprises C54-titanium silicide. Word line stacks formed by the methods of the invention are used in sub-0.25 micron line width applications and have a lower resistivity and improved thermal stability.

公开(公告)号：US09530674B2

公开(公告)日：2016-12-27

申请号：US14044138

申请日：2013-10-02

申请人： Ellie Yieh ,  Ludovic Godet ,  Srinivas Nemani ,  Er-Xuan Ping ,  Gary Dickerson

发明人： Ellie Yieh ,  Ludovic Godet ,  Srinivas Nemani ,  Er-Xuan Ping ,  Gary Dickerson

IPC分类号： H01L21/00 ,  H01L21/67 ,  C23C14/02 ,  C23C14/04 ,  C23C16/02 ,  C23C16/04 ,  H01L21/02

CPC分类号： H01L21/02271 ,  C23C14/021 ,  C23C14/046 ,  C23C16/0227 ,  C23C16/045 ,  C23C16/45544 ,  C23C16/50 ,  H01J37/32009 ,  H01J2237/334 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02315 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/67017 ,  H01L21/67213 ,  H01L21/76224

摘要： Embodiments include methods and systems of 3D structure fill. In one embodiment, a method of filling a trench in a wafer includes performing directional plasma treatment with an ion beam at an angle with respect to a sidewall of the trench to form a treated portion of the sidewall and an untreated bottom of the trench. A material is deposited in the trench. The deposition rate of the material on the treated portion of the sidewall is different than a second deposition rate on the untreated bottom of the trench. In one embodiment, a method includes depositing a material on the wafer, filling a bottom of the trench and forming a layer on a sidewall of the trench and a top surface adjacent to the trench. The method includes etching the layer with an ion beam at an angle with respect to the sidewall.

摘要翻译： 实施例包括3D结构填充的方法和系统。 在一个实施例中，在晶片中填充沟槽的方法包括使用离子束相对于沟槽的侧壁以一定角度执行定向等离子体处理，以形成侧壁的处理部分和沟槽的未处理底部。 材料沉积在沟槽中。 材料在侧壁的处理部分上的沉积速率不同于沟槽的未处理底部上的第二沉积速率。 在一个实施例中，一种方法包括在晶片上沉积材料，填充沟槽的底部并在沟槽的侧壁上形成层，以及邻近沟槽的顶表面。 该方法包括用相对于侧壁成一定角度的离子束蚀刻该层。

公开(公告)号：US08866124B2

公开(公告)日：2014-10-21

申请号：US13020007

申请日：2011-02-02

申请人： Steven Maxwell ,  Abhijit Bandyopadhyay ,  Kun Hou ,  Er-Xuan Ping ,  Yung-Tin Chen ,  Li Xiao

发明人： Steven Maxwell ,  Abhijit Bandyopadhyay ,  Kun Hou ,  Er-Xuan Ping ,  Yung-Tin Chen ,  Li Xiao

IPC分类号： H01L47/00 ,  H01L29/868 ,  H01L27/102

CPC分类号： H01L27/1021 ,  H01L29/868 ,  Y10S438/90

摘要： In a first aspect, a vertical semiconductor diode is provided that includes (1) a first semiconductor layer formed above a substrate; (2) a second semiconductor layer formed above the first semiconductor layer; (3) a first native oxide layer formed above the first semiconductor layer; and (4) a third semiconductor layer formed above the first semiconductor layer, second semiconductor layer and first native oxide layer so as to form the vertical semiconductor diode that includes the first native oxide layer. Numerous other aspects are provided.

摘要翻译： 在第一方面，提供一种垂直半导体二极管，其包括：（1）形成在基板上的第一半导体层; （2）形成在第一半导体层上方的第二半导体层; （3）形成在所述第一半导体层上方的第一自然氧化物层; 以及（4）形成在第一半导体层上的第三半导体层，第二半导体层和第一自然氧化物层，以形成包括第一自然氧化物层的垂直半导体二极管。 提供了许多其他方面。

公开(公告)号：US20130320542A1

公开(公告)日：2013-12-05

申请号：US13986499

申请日：2013-05-08

申请人： Chorng-Ping Chang ,  Bingxi Wood ,  Er-Xuan Ping

发明人： Chorng-Ping Chang ,  Bingxi Wood ,  Er-Xuan Ping

IPC分类号： H01L21/768 ,  H01L23/498

CPC分类号： H01L21/76889 ,  H01L21/743 ,  H01L23/498 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a self-aligned buried bit line in a structure which makes up a portion of a vertical channel DRAM. The materials and processes used enable self-alignment of elements of the buried bit line during the fabrication process. In addition, the materials and processes used enable for formation of individual DRAM cells which have a buried bit line width which is 16 nm or less.

摘要翻译： 在构成垂直通道DRAM的一部分的结构中制造自对准埋入位线的方法。 所使用的材料和工艺在制造过程中能够对掩埋位线的元件进行自对准。 此外，所使用的材料和工艺能够形成具有16nm或更小的掩埋位线宽度的各个DRAM单元。

公开(公告)号：US08470646B2

公开(公告)日：2013-06-25

申请号：US12650417

申请日：2009-12-30

申请人： Huiwen Xu ,  Xiying Chen ,  Er-Xuan Ping

发明人： Huiwen Xu ,  Xiying Chen ,  Er-Xuan Ping

IPC分类号： H01L21/332 ,  H01L21/20 ,  H01L29/02 ,  H01L47/00

CPC分类号： G11C13/00 ,  G11C13/0004 ,  G11C2213/35 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/149 ,  H01L45/1616

摘要： In a first aspect, a method of forming a memory cell is provided that includes (1) forming a metal-insulator-metal (“MIM”) stack above a substrate, the MIM stack including a carbon-based switching material having a resistivity of at least 1×104 ohm-cm; and (2) forming a steering element coupled to the MIM stack. Numerous other aspects are provided.

摘要翻译： 在第一方面，提供一种形成存储单元的方法，其包括：（1）在衬底上形成金属 - 绝缘体 - 金属（“MIM”）堆叠，所述MIM堆叠包括具有电阻率的碳基开关材料 至少1×104欧姆厘米; 和（2）形成耦合到所述MIM堆叠的操纵元件。 提供了许多其他方面。

公开(公告)号：US08120124B2

公开(公告)日：2012-02-21

申请号：US11712077

申请日：2007-02-28

申请人： Lingyi A. Zheng ,  Er-Xuan Ping

发明人： Lingyi A. Zheng ,  Er-Xuan Ping

IPC分类号： H01L21/00

CPC分类号： H01L21/0217 ,  C23C16/0272 ,  C23C16/345 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/31051 ,  H01L21/3115 ,  H01L21/3185 ,  H01L21/3211 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming silicon nitride films on semiconductor devices is provided. In one embodiment of the method, a silicon-comprising substrate is first exposed to a mixture of dichlorosilane (DCS) and a nitrogen-comprising gas to deposit a thin silicon nitride seeding layer on the surface, and then exposed to a mixture of silicon tetrachloride (TCS) and a nitrogen comprising gas to deposit a TCS silicon nitride layer on the DCS seeding layer. In another embodiment, the method involves first nitridizing the surface of the silicon-comprising substrate prior to forming the DCS nitride seeding layer and the TCS nitride layer. The method achieves a TCS nitride layer having a sufficient thickness to eliminate bubbling and punch-through problems and provide high electrical performance regardless of the substrate type. Also provided are methods of forming a capacitor, and the resulting capacitor structures.

摘要翻译： 提供了一种在半导体器件上形成氮化硅膜的方法。 在该方法的一个实施方案中，首先将含硅衬底暴露于二氯硅烷（DCS）和含氮气体的混合物以在表面上沉积薄氮化硅接种层，然后暴露于四氯化硅 （TCS）和包含气体的氮气以在DCS籽晶层上沉积TCS氮化硅层。 在另一个实施方案中，该方法包括在形成DCS氮化物接种层和TCS氮化物层之前首先氮化含硅衬底的表面。 该方法实现了具有足够厚度的TCS氮化物层，以消除起泡和穿通问题，并且不管衬底类型如何，都能提供高电性能。 还提供了形成电容器的方法以及所得到的电容器结构。