公开(公告)号：US20060138639A1

公开(公告)日：2006-06-29

申请号：US11024059

申请日：2004-12-28

申请人： David Figueroa ,  Jennifer Hester ,  Yuan-Liang Li

发明人： David Figueroa ,  Jennifer Hester ,  Yuan-Liang Li

IPC分类号： H01L23/12

CPC分类号： H01L23/49827 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/01079 ,  H01L2924/15312 ,  H01L2924/19103 ,  H01L2924/19106 ,  H05K1/0231 ,  H05K1/113 ,  H05K3/4644 ,  H05K2201/09627 ,  H05K2201/097 ,  H05K2201/09709

摘要： According to some embodiments, an apparatus includes a first conductive pad, a first conductive plane, first dielectric material disposed between the first conductive plane and the first conductive pad, a second conductive plane, second dielectric material disposed between the first conductive plane and the second conductive plane, and a first conductive network. The first conductive network includes a first microvia within the first dielectric material and coupled to the first conductive pad, a first conductive trace within the first conductive plane and coupled to the first microvia, a second microvia within the second dielectric material and coupled to the first conductive trace, a second conductive trace within the second conductive plane and coupled to the second microvia, a third microvia within the second dielectric material and coupled to the second conductive trace, a third conductive trace within the first conductive plane and coupled to the third microvia, and a fourth microvia within the second dielectric material and coupled to the third conductive trace.

摘要翻译： 根据一些实施例，装置包括第一导电焊盘，第一导电平面，设置在第一导电平面和第一导电焊盘之间的第一电介质材料，第二导电平面，第二电介质材料，设置在第一导电平面和第二导电平面之间 导电平面和第一导电网络。 所述第一导电网络包括所述第一电介质材料内的第一微孔并且耦合到所述第一导电焊盘，所述第一导电平面内的第一导电迹线并耦合到所述第一微孔，所述第二介电材料内的第二微孔， 导电迹线，第二导电平面内的第二导电迹线，并且耦合到第二微孔，在第二介电材料内的第三微孔并耦合到第二导电迹线，第一导电平面内的第三导电迹线并耦合到第三微孔 以及在第二电介质材料内的第四微孔并且耦合到第三导电迹线。

公开(公告)号：US06948943B2

公开(公告)日：2005-09-27

申请号：US10090796

申请日：2002-03-06

申请人： Yuan-Liang Li

发明人： Yuan-Liang Li

IPC分类号： H01R31/08 ,  H05K7/10 ,  H05K1/14

CPC分类号： H01R31/08 ,  H01R12/523 ,  H05K7/1092

摘要： A shunt connector is provided to electrically couple two electrical components mountable together via a grid array. The connector may provide mechanical support and provides a shunt electrical conduction path to increase current-carrying capacity between the electrical components of the grid array. In an embodiment, at least part of the shunt connector may extend within one of the electrical components so as to provide the shunt electrical conduction path.

摘要翻译： 提供分流连接器以电耦合通过网格阵列可安装在一起的两个电气部件。 连接器可以提供机械支撑并且提供并联导电路径以增加电网阵列的电气部件之间的载流能力。 在一个实施例中，分流连接器的至少一部分可以在电气部件之一内延伸，以便提供分流导电路径。

公开(公告)号：US20050194675A1

公开(公告)日：2005-09-08

申请号：US11103939

申请日：2005-04-12

申请人： Jennifer Hester ,  Yuan-Liang Li ,  Michael Desmith ,  David Figueroa ,  Dong Zhong

发明人： Jennifer Hester ,  Yuan-Liang Li ,  Michael Desmith ,  David Figueroa ,  Dong Zhong

IPC分类号： H01G4/38 ,  H01L23/498 ,  H01L23/64 ,  H05K1/02 ,  H05K1/11 ,  H01L23/48

CPC分类号： H05K1/114 ,  H01G4/385 ,  H01L23/49838 ,  H01L23/642 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/01057 ,  H01L2924/15312 ,  H01L2924/19106 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K2201/09263 ,  H05K2201/09345 ,  H05K2201/0979 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2224/0401

摘要： According to some embodiments, a device includes a first conductive plane electrically coupled to a first terminal associated with a first polarity and a second terminal associated with the first polarity, a second conductive plane electrically coupled to a third terminal associated with a second polarity, and a dielectric disposed between the first conductive plane and the second conductive plane. A first capacitance is present between the first terminal and the third terminal, a second capacitance is present between the second terminal and the third terminal, and the first capacitance and the second capacitance may be substantially dissimilar.

摘要翻译： 根据一些实施例，器件包括电耦合到与第一极性相关联的第一端子的第一导电平面和与第一极性相关联的第二端子，电耦合到与第二极性相关联的第三端子的第二导电平面，以及 设置在所述第一导电平面和所述第二导电平面之间的电介质。 在第一端子和第三端子之间存在第一电容，在第二端子和第三端子之间存在第二电容，并且第一电容和第二电容可以是基本不相似的。

公开(公告)号：US06907658B2

公开(公告)日：2005-06-21

申请号：US10635877

申请日：2003-08-05

申请人： Yuan-Liang Li

发明人： Yuan-Liang Li

IPC分类号： H01L23/12 ,  H01L23/498 ,  H01L23/50 ,  H01L23/64 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H03K3/30

CPC分类号： H01L23/49822 ,  H01L23/50 ,  H01L23/642 ,  H01L2224/16225 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/19106 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/162 ,  H05K1/185 ,  H05K2201/09309 ,  H05K2201/10545 ,  H05K2201/10734 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49117 ,  Y10T29/4913

摘要： An electronic assembly includes one or more discrete capacitors (506, 804, 1204), which are vertically connected to a housing, such as an integrated circuit package (1704). Surface mounted capacitors (506) are vertically connected to pads (602) on a top or bottom surface of the package. Embedded capacitors (804, 1204) are vertically connected to vias (808, 816, 1210, and/or 1212) or other conductive structures within the package. Vertically connecting a surface mounted or embedded capacitor involves aligning (1604) side segments (416) of some of the capacitor's terminals with the conductive structures (e.g., pads, vias or other structures) so that the side of the capacitor upon which the side segments reside is substantially parallel with the top or bottom surface of the package. Where a capacitor includes extended terminals (1208), the capacitor can be embedded so that the extended terminals provide additional current shunts through the package.

摘要翻译： 电子组件包括垂直连接到诸如集成电路封装（1704）的壳体的一个或多个分立电容器（506,804,1204）。 表面安装电容器（506）垂直连接到封装的顶表面或底表面上的焊盘（602）。 嵌入式电容器（804,1204）垂直连接到封装内的通孔（808,816,1210和/或1212）或其他导电结构。 垂直连接表面安装或嵌入式电容器包括将电容器端子中的一些端子（1604）与导电结构（例如，焊盘，通孔或其它结构）对准（1604），使得电容器的侧面 驻极体基本上平行于包装的顶部或底部表面。 在电容器包括延伸端子（1208）的情况下，可以嵌入电容器，使得延伸端子通过封装件提供额外的电流分路。

公开(公告)号：US06841842B2

公开(公告)日：2005-01-11

申请号：US10649414

申请日：2003-08-26

申请人： Yuan-Liang Li

发明人： Yuan-Liang Li

IPC分类号： G02B6/42 ,  G02B6/43 ,  H01L31/12 ,  H01L31/00

CPC分类号： G02B6/43 ,  G02B6/4232 ,  H01L31/12 ,  H01L2224/16225

摘要： An optical-electrical (OE) package includes a substrate electrically coupled to a motherboard via one or more capacitor DC shunts (CDCSs). In one embodiment, the substrate includes an IC chip electrically coupled to a first set of contact-receiving members on an upper surface of the substrate. The substrate also includes a light-emitting package and a photodetector package electrically coupled to respective second and third sets of contact-receiving members on the substrate lower surface. The substrate has internal wiring that electrically interconnects the IC chip, the light-emitting package and the photodetector array. The light-emitting package and the photodetector array are optically coupled to respective first and second waveguide arrays formed in or on the motherboard. The CDCSs mitigate noise generated by the IC chip by serving as a local current source.

摘要翻译： 光电（OE）封装包括经由一个或多个电容器DC分流器（CDCS）电耦合到母板的基板。 在一个实施例中，衬底包括电连接到衬底的上表面上的第一组接触件的IC芯片。 衬底还包括发光封装和光电检测器封装，电耦合到衬底下表面上相应的第二组和第三组接触件。 衬底具有将IC芯片，发光封装和光电检测器阵列电互连的内部布线。 发光封装和光电检测器阵列光学耦合到形成在母板中或母板上的相应的第一和第二波导阵列。 CDCS通过作为本地电流源来减轻由IC芯片产生的噪声。

公开(公告)号：US06599031B2

公开(公告)日：2003-07-29

申请号：US09949926

申请日：2001-09-12

申请人： Yuan-Liang Li

发明人： Yuan-Liang Li

IPC分类号： G02B612

CPC分类号： G02B6/43 ,  G02B6/4201 ,  G02B6/4246 ,  G02B6/4249 ,  G02B6/4279 ,  G02B6/428 ,  H05K1/0274

摘要： An opto-electrical printed circuit board (PCB) and compatible opto-electrical package. The PCB includes a base material, one or more optical fibers imbedded in or on top of the base material, and one or more transparent substrates imbedded in or on top of the base material covering the optical fibers. The optical fibers provide a high speed interconnect between two or more electronic devices attached to the PCB. The electronic devices interface to the optical fibers through the transparent substrate. The opto-electrical package includes a base material, an optical receiver and an optical transmitter attached to the bottom side of the base material, an encapsulating polymer that covers the optical receiver and optical transmitter, and one or more power and ground connection points attached to the bottom side of the base material.

摘要翻译： 光电印刷电路板（PCB）和兼容的光电封装。 PCB包括基材，嵌入在基材中或其上的一个或多个光纤，以及嵌入在覆盖光纤的基材的顶部或之上的一个或多个透明基板。 光纤提供了连接到PCB的两个或多个电子设备之间的高速互连。 电子设备通过透明基板与光纤接口。 光电封装包括基材，光接收器和连接到基底材料的底侧的光发射器，覆盖光接收器和光发送器的封装聚合物，以及一个或多个电源和接地连接点 基材的底面。

公开(公告)号：US06495770B2

公开(公告)日：2002-12-17

申请号：US09730210

申请日：2000-12-04

申请人： Yuan-Liang Li ,  David G. Figueroa ,  Priyavadan R. Patel

发明人： Yuan-Liang Li ,  David G. Figueroa ,  Priyavadan R. Patel

IPC分类号： H05K111

CPC分类号： H01L23/49822 ,  H01L23/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/15312 ,  H01L2224/05599

摘要： The invention provides an electronic assembly including a semiconductor chip and a semiconductor package substrate having power and ground shunts. The power and ground shunts of the semiconductor chip include contact pads on a surface thereof that are electrically connected to one another to protect electrical signal contacts on the contact pads from high, low-frequency current. The power shunt in the semiconductor package substrate connects one power plane to another and the ground shunts in the semiconductor package substrate connects one ground plane to another. The power and ground shunts in the semiconductor package substrate dictate terminal pins thereon from high, low-frequency current.

公开(公告)号：US20140266490A1

公开(公告)日：2014-09-18

申请号：US13844761

申请日：2013-03-15

申请人： Kai Xiao ,  Jimmy Hsu ,  Yuan-Liang Li ,  Richard K. Kunze

发明人： Kai Xiao ,  Jimmy Hsu ,  Yuan-Liang Li ,  Richard K. Kunze

IPC分类号： H05K1/02 ,  H01P11/00 ,  H01P3/08

CPC分类号： H05K1/0228 ,  H01P3/08 ,  H01P11/00 ,  H05K1/0245 ,  H05K1/0298 ,  H05K2201/09236 ,  H05K2201/09709 ,  Y10T29/49155

摘要： A signal line design is described herein. A circuit board may include a first signal line and a second signal line. The first signal line includes a pair of signal lines at a first depth of a section of a circuit board, wherein a centerline extends lengthwise between the pair of signal lines. The second signal line is disposed at a second depth of the circuit board. The second signal line includes a first segment that runs parallel to the first signal line at a first displacement from the center line. The second signal line includes a second segment that runs parallel to the first signal line on the other side of the center line at a second displacement distance from the center line.

摘要翻译： 这里描述了信号线设计。 电路板可以包括第一信号线和第二信号线。 第一信号线包括在电路板的一部分的第一深度处的一对信号线，其中中心线在该对信号线之间纵向延伸。 第二信号线设置在电路板的第二深度处。 第二信号线包括第一段，该第一段在与中心线的第一位移处平行于第一信号线延伸。 第二信号线包括与中心线的另一侧平行于第一信号线的第二段，距中心线的第二位移距离。

公开(公告)号：US07518248B2

公开(公告)日：2009-04-14

申请号：US11462611

申请日：2006-08-04

申请人： Yuan-Liang Li ,  David G. Figueroa

发明人： Yuan-Liang Li ,  David G. Figueroa

IPC分类号： H01L23/52

CPC分类号： H01F17/0033 ,  H01F41/041 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15312 ,  H05K1/115 ,  H05K1/165 ,  H05K3/06 ,  H05K3/42 ,  H05K2201/086 ,  H05K2201/097 ,  H05K2201/1006 ,  H05K2203/0723 ,  H01L2224/0401

摘要： A series of plated through hole (PTH) vias are interconnected by traces that alternate between a top surface and a bottom surface of a dielectric board. The PTH vias in the series can be positioned to create a collinear inductive filter, a coil-type inductive filter, or a transformer. Multiple, electrically isolated series of interconnected PTH vias can be used as a multi-phase inductive filter in one embodiment. In another embodiment, multiple series of interconnected PTH vias are electrically connected by a linking portion of conductive material, resulting in a low-resistance inductive filter. Ferromagnetic material patterns can be embedded in the dielectric board to enhance the inductive characteristics of the interconnected via structures. In one embodiment, a closed-end pattern is provided with two series of interconnected vias coiling around the pattern, resulting in an embedded transformer structure. A method of producing an interconnected series of PTH vias includes providing a dielectric board having a series of holes. In some embodiments, the board includes an embedded ferromagnetic material pattern. The holes and the top and bottom surface of the dielectric board have a conductive material thereupon. Portions of the conductive material are selectively removed, resulting in the embedded inductive filter and/or transformer structure.

摘要翻译： 一系列电镀通孔（PTH）通孔在电介质板的顶表面和底表面之间交替的迹线互连。 该系列中的PTH通孔可以定位成产生共线感应滤波器，线圈型感应滤波器或变压器。 在一个实施例中，多个电隔离的互连PTH通孔系列可用作多相感应滤波器。 在另一个实施例中，多个互连的PTH通孔系列通过导电材料的连接部分电连接，导致低电阻感应滤波器。 铁磁材料图案可以嵌入电介质板中以增强互连通孔结构的感应特性。 在一个实施例中，闭合端图案具有围绕图案卷绕的两系列互连的通孔，从而形成嵌入式变压器结构。 制造互连的PTH通孔系列的方法包括提供具有一系列孔的电介质板。 在一些实施例中，板包括嵌入的铁磁材料图案。 电介质板的孔和顶表面和底表面之间具有导电材料。 选择性地去除导电材料的部分，从而产生嵌入的感应滤波器和/或变压器结构。

公开(公告)号：US07492605B2

公开(公告)日：2009-02-17

申请号：US11473359

申请日：2006-06-22

申请人： Yuan-Liang Li ,  Jayashree Kar ,  David G. Figueroa ,  Dong Zhong

发明人： Yuan-Liang Li ,  Jayashree Kar ,  David G. Figueroa ,  Dong Zhong

IPC分类号： H05K1/11 ,  H05K1/00

CPC分类号： H05K1/0265 ,  H05K1/0254 ,  H05K2201/044 ,  H05K2201/0784 ,  H05K2201/093 ,  H05K2201/0969

摘要： A power plane including a supply power pin receptacle, a first connector power pin receptacle, and a second power pin receptacle, where a first electrical resistance between the supply power pin receptacle and the first connector power pin receptacle is substantially equal to a second electrical resistance between the supply power pin receptacle and the second connector power pin receptacle.

摘要翻译： 包括供电电源插座，第一连接器电源插座和第二电源插座的电力平面，其中电源电极插座和第一连接器电源插座之间的第一电阻基本上等于第二电阻 在电源插座和第二连接器电源插座之间。