公开(公告)号：US20140233325A1

公开(公告)日：2014-08-21

申请号：US14265852

申请日：2014-04-30

Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

Inventor： Jin-Ki KIM ,  HakJune OH

IPC: G11C11/406

CPC classification number: G11C11/40615 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/40618 ,  G11C11/40622

Abstract: A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application.

Abstract translation: 动态随机存取存储器件包括多个存储器子块。 每个子块具有连接多个数据存储单元的多个字线。 部分阵列自刷新（PASR）配置设置是独立制作的。 根据PASR设置，内存子块被寻址以进行刷新。 PASR设置由内存控制器进行。 可以选择子块地址的任何种类的组合。 因此，存储器子块被完全独立地刷新。 用于数据保留的用户可选择的存储器阵列提供有效的存储器控​​制编程，特别是对于低功率

公开(公告)号：US08782590B2

公开(公告)日：2014-07-15

申请号：US13164362

申请日：2011-06-20

Applicant: Barry Alan Hoberman ,  Daniel L. Hillman ,  Jon Shiell

Inventor： Barry Alan Hoberman ,  Daniel L. Hillman ,  Jon Shiell

IPC: H02J1/00 ,  G06F17/50

CPC classification number: H03K3/012 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  H01L2924/00 ,  H01L2924/0002 ,  H02J4/00 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20 ,  Y10T307/406 ,  Y10T307/414

Abstract: A system for an integrated circuit comprising a plurality of power islands includes a first power manager and a second power manager. The first power manager manages a first power consumption for the integrated circuit based on needs and operation of the integrated circuit. The second power manager communicates with the first power manager and manages a second power consumption for one of the power islands.

公开(公告)号：US08743610B2

公开(公告)日：2014-06-03

申请号：US13171667

申请日：2011-06-29

Applicant: Jin-Ki Kim ,  Hong Beom Pyeon

Inventor： Jin-Ki Kim ,  Hong Beom Pyeon

IPC: G11C16/00

CPC classification number: G06F3/0611 ,  G06F3/0655 ,  G06F3/0688 ,  G06F13/4243 ,  G11C5/066 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/10 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459 ,  G11C2207/107 ,  G11C2216/30

Abstract: An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

Abstract translation: 公开了一种用于控制半导体存储器中的多个串行数据链路接口和多个存储体之间的数据传输的装置，系统和计算机实现的方法。 在一个示例中，公开了具有多个链路和存储体的闪存器件，其中链路独立于存储体。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。 此外，描述了虚拟多链路配置，其中使用单个链路来模拟多个链路。

公开(公告)号：US08737105B2

公开(公告)日：2014-05-27

申请号：US13091465

申请日：2011-04-21

Applicant: Jin-Ki Kim

Inventor： Jin-Ki Kim

IPC: G11C5/02

CPC classification number: G11C7/00 ,  G11C5/02 ,  G11C5/025

Abstract: Bridge device architecture for connecting discrete memory devices is disclosed. A bridge device is used in conjunction with a composite memory device including at least one discrete memory device. The bridge device comprises a local control interface connected to the at least one discrete memory device, a local input/output interface connected to the at least one discrete memory device, and a global input/output interface interposed between the local control interface and the local input/output interface. The global input/output interface receives and provides global memory control signals and also receives and provides write data to and read data from the at least one discrete memory device.

Abstract translation: 公开了用于连接分立存储器件的桥接器件架构。 桥接器件与包括至少一个分立存储器件的复合存储器件结合使用。 桥接器件包括连接到至少一个分立存储器件的本地控制接口，连接到至少一个分立存储器件的本地输入/输出接口以及插入在本地控制接口和本地之间的全局输入/输出接口 输入/输出接口。 全局输入/输出接口接收并提供全局存储器控制信号，并且还接收并向至少一个离散存储器件提供写入数据和从其读取数据。

公开(公告)号：US20210142857A1

公开(公告)日：2021-05-13

申请号：US17154241

申请日：2021-01-21

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Chung-Zen CHEN ,  Yang-Chieh LIN ,  Chung-Shan KUO

IPC: G11C16/14 ,  G11C16/16 ,  G11C16/08 ,  G11C16/02 ,  G11C16/04

Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal

公开(公告)号：US20210132799A1

公开(公告)日：2021-05-06

申请号：US16950204

申请日：2020-11-17

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Peter B. Gillingham ,  Graham Allan

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G11C16/10 ,  G11C16/28 ,  G11C16/32 ,  G11C16/04 ,  G11C14/00

Abstract: A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

公开(公告)号：US10998048B2

公开(公告)日：2021-05-04

申请号：US16580099

申请日：2019-09-24

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Hyoung Seub Rhie

IPC: G11C16/14 ,  G11C16/06

Abstract: A non-volatile memory device using existing row decoding circuitry to selectively provide a global erase voltage to at least one selected memory block in order to facilitate erasing of all the non-volatile memory cells of the at least one selected memory block. More specifically, the erase voltage is coupled to the cell body or substrate of memory cells of the at least one selected memory block, where the cell body is electrically isolated from the cell body of non-volatile memory cells in at least one other memory block. By integrating the erase voltage path with the existing row decoding circuitry used to drive row signals for a selected memory block, no additional decoding logic or circuitry is required for providing the erase voltage to the at least one selected memory block.

公开(公告)号：US20210036689A1

公开(公告)日：2021-02-04

申请号：US16928311

申请日：2020-07-14

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Barry Alan HOBERMAN ,  Daniel L. HILLMAN ,  Jon Shiell

IPC: H03K3/012 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  H02J4/00

Abstract: Systems and methods manage power in an integrated circuit using power islands. The integrated circuit includes a plurality of power islands wherein a power consumption of each power island within the plurality of power islands is independently controlled within each of the power islands. A power manager determines a target power level for one power island of the plurality of power islands. The power manager then determines an action to change a consumption power level of the one power island of the plurality of power islands to the target power level. The power manager performs the action to change the consumption power level of the one power island of the plurality of power islands to the target power level.

公开(公告)号：USRE48410E1

公开(公告)日：2021-01-26

申请号：US14209455

申请日：2014-03-13

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Randy J. Caplan ,  Steven J. Schwake

IPC: G05F1/10 ,  H03K19/00

Abstract: A leakage manager system for adequately minimizing static leakage of an integrated circuit is disclosed. The leakage manager system includes a generator configured to generate a control signal to be applied to a sleep transistor. A monitor is configured to determine whether to adjust the control signal to adequately minimize the static leakage. In some embodiments, the monitor includes an emulated sleep transistor. A regulator is configured to adjust the control signal depending on the determination.

公开(公告)号：US10749506B2

公开(公告)日：2020-08-18

申请号：US16226917

申请日：2018-12-20

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Barry Alan Hoberman ,  Daniel L. Hillman ,  Jon Shiell

IPC: H03K3/012 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  H02J4/00

Abstract: Systems and methods manage power in an integrated circuit using power islands. The integrated circuit includes a plurality of power islands wherein a power consumption of each power island within the plurality of power islands is independently controlled within said each power island. A power manager determines a target power level for one power island of the plurality of power islands. The power manager then determines an action to change a consumption power level of said one power island of the plurality of power islands to the target power level. The power manager performs the action to change the consumption power level of said one power island of the plurality of power islands to the target power level.