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    Link and message management improvements
    42.
    发明授权
    Link and message management improvements 有权

    公开(公告)号：US09769751B2

    公开(公告)日：2017-09-19

    申请号：US14298983

    申请日：2014-06-09

    Applicant: DSP Group LTD.

    Inventor： Oleg Maizlish ,  Ido Achrak

    IPC: H04W4/12 ,  H04W52/02 ,  H04W72/12

    CPC classification number: H04W52/0216 ,  H04W4/12 ,  H04W52/0209 ,  H04W72/121 ,  Y02D70/142

    Abstract: A method for transferring messages to wireless communication device, the method may include receiving, by an intermediate device, from a upstream device, a certain message awaiting indication that is indicative that a certain message is waiting to be sent to a certain wireless communication device; detecting, by the intermediate device, that the certain wireless communication device is in a wireless communication facilitating mode; requesting the certain wireless communication device, to re-enter the wireless communication facilitating mode at a certain time frame; retrieving the certain message from the upstream device; detecting, by the intermediate device, that the certain wireless communication device re-entered the wireless communication facilitating mode at the certain time frame; and wirelessly transmitting the certain message to the certain wireless communication device.

    Method and apparatus for ultra-low power switching microphone
    44.
    发明授权
    Method and apparatus for ultra-low power switching microphone 有权

    公开(公告)号：US09602920B2

    公开(公告)日：2017-03-21

    申请号：US14600026

    申请日：2015-01-20

    Applicant: DSP Group LTD.

    Inventor： Moshe Haiut

    IPC: H03F99/00 ,  H04R3/00 ,  H04R1/04

    CPC classification number: H04R3/00 ,  H04R1/04 ,  H04R2201/003

    Abstract: A scheme is described to switch the power supply to the MEMS microphone on and off in a cyclic manner that is synchronized with the associated ADC sampling rate. In this way the MEMS microphone amplifier, whether it is a J-FET transistor or an operational amplifier, is off most of the cycle time, and is turned on only for a few micro-seconds prior to the sample-and-hold timing of the ADC device. By this method, the average power consumption of an existing analog MEMS microphone can be reduced by a factor of 10 or more.

    Dynamic gain switching digital to analog converter
    46.
    发明授权
    Dynamic gain switching digital to analog converter 有权
    动态增益切换数模转换器

    公开(公告)号：US09143157B1

    公开(公告)日：2015-09-22

    申请号：US14630817

    申请日：2015-02-25

    Applicant: DSP Group LTD.

    Inventor： Ori Elyada

    IPC: H03M1/66 ,  H03M1/70 ,  H03M1/00 ,  H03M1/08

    CPC classification number: H03M1/70 ,  H03M1/662

    Abstract: A digital to analog converter that may include a digital gain block; an analog gain block; a digital to analog conversion (DAC) block and a controller that is configured to: determine a digital gain factor, selected out of multiple digital gain factors, of the digital gain block and an analog gain factor, selected out of multiple analog gain factors of the analog gain block; wherein the DAC block is preceded by the digital gain block and is followed by the analog gain block; wherein the digital gain block is configured to multiply a digital input signal by the digital gain factor to provide an intermediate digital signal; wherein the DAC block is configured to convert the intermediate digital signal to a converted analog signal; and wherein the analog gain block is configured to multiply the converted analog signal by the analog gain factor to provide an output signal; wherein an increment of the analog gain factor results in a decrement of the digital gain factor.

    Abstract translation: 可以包括数字增益块的数模转换器; 模拟增益块 数模转换（DAC）块和控制器，其被配置为：确定数字增益块的多个数字增益因子中选择的数字增益因子和从多个模拟增益因子中选择的模拟增益因子 模拟增益块; 其中DAC块前面是数字增益块，后面是模拟增益块; 其中所述数字增益块被配置为将数字输入信号乘以所述数字增益因子以提供中间数字信号; 其中所述DAC块被配置为将所述中间数字信号转换为转换的模拟信号; 并且其中所述模拟增益块被配置为将所述转换的模拟信号乘以所述模拟增益因子以提供输出信号; 其中模拟增益因子的增量导致数字增益因子的减小。

    Adaptive system for managing a plurality of microphones and speakers
    47.
    发明授权
    Adaptive system for managing a plurality of microphones and speakers 有权
    用于管理多个麦克风和扬声器的自适应系统

    公开(公告)号：US09124965B2

    公开(公告)日：2015-09-01

    申请号：US14074365

    申请日：2013-11-07

    Applicant: DSP Group

    Inventor： Arie Heiman ,  Uri Yehuday ,  Roei Roeimi

    IPC: H04R29/00 ,  H04R1/00 ,  H04R3/00

    CPC classification number: H04R1/00 ,  H04R3/00 ,  H04R2400/01 ,  H04R2499/11

    Abstract: Methods and systems are provided for adaptively managing a plurality of microphones and speakers in an electronic device. A mode of operation of the electronic device may be determined, and operation of at least one speaker may be managed, based on the determined mode of operation. The managing may comprise adaptively switching or modifying functions of the at least one speaker. For example, the at least one speaker may be configured to act as microphone or as vibration detector. Input obtained using the at least one speaker may be utilized in optimizing audio related functions, such as noise reduction and/or acoustic echo canceling.

    Abstract translation: 提供了用于在电子设备中自适应地管理多个麦克风和扬声器的方法和系统。 可以基于确定的操作模式来确定电子设备的操作模式，并且可以管理至少一个扬声器的操作。 管理可以包括自适应地切换或修改至少一个扬声器的功能。 例如，至少一个扬声器可被配置为充当麦克风或作为振动检测器。 使用至少一个扬声器获得的输入可以用于优化诸如降噪和/或声学回声消除之类的音频相关功能。

    CONFIGURABLE MULTIMODE MULTIBAND INTEGRATED DISTRIBUTED POWER AMPLIFIER
    48.
    发明申请
    CONFIGURABLE MULTIMODE MULTIBAND INTEGRATED DISTRIBUTED POWER AMPLIFIER 审中-公开
    可配置多模多路集成分布式功率放大器

    公开(公告)号：US20150070097A1

    公开(公告)日：2015-03-12

    申请号：US14540687

    申请日：2014-11-13

    Applicant: DSP Group, Ltd.

    Inventor： Abraham Bauer ,  Eli Schwartz ,  Ilya Sima ,  Lior Blanka ,  Sergey Anderson ,  Ron Pongratz ,  Alex Mostov

    IPC: H03F3/21 ,  H04B1/04 ,  H04W88/06 ,  H03F1/02 ,  H03F3/193

    CPC classification number: H03F3/211 ,  H03F1/02 ,  H03F1/0227 ,  H03F1/0261 ,  H03F3/19 ,  H03F3/193 ,  H03F3/21 ,  H03F3/24 ,  H03F3/45179 ,  H03F2200/102 ,  H03F2200/105 ,  H03F2200/451 ,  H03F2200/534 ,  H03F2200/537 ,  H03F2200/541 ,  H04B1/04 ,  H04B2001/045 ,  H04W88/06

    Abstract: A novel and useful configurable radio frequency (RF) power amplifier (PA) and related front end module (FEM) circuit that enables manipulation of the operating point of the power amplifier resulting in configurability, multimode and multiband operating capability. The configurable PA also provides high linearity and power efficiency and meets the requirements of modern wireless communication standards such as 802.11 WLAN, 3G and 4G cellular standards, Bluetooth, ZigBee, etc. The configurable power amplifier is made up of one or more configurable sub-amplifiers having each constructed to have several orders of freedom (i.e. biasing points). Each sub-amplifier and its combiner path include active and passive elements. Manipulating one or more biasing points of each sub-amplifier, and therefore of the aggregate power amplifier as well, achieves multimode and multiband operation. Biasing points include, for example, the gain and saturation point, frequency response, linearity level and EVM. An integrated multi-tap transformer having primary and secondary windings arranged in a novel configuration provides efficient power combining and transfer to the antenna of the power generated by the individual sub-amplifiers.

    Abstract translation: 一种新颖有用的可配置射频（RF）功率放大器（PA）和相关的前端模块（FEM）电路，可以对功率放大器的工作点进行操作，从而实现可配置性，多模和多频带操作能力。 可配置PA还提供高线性度和功率效率，并满足现代无线通信标准（如802.11 WLAN，3G和4G蜂窝标准，蓝牙，ZigBee等）的要求。可配置功率放大器由一个或多个可配置子系统组成， 每个放大器被构造成具有几个自由度（即偏置点）。 每个子放大器及其组合器路径包括有源和无源元件。 操纵每个子放大器的一个或多个偏置点，并因此操纵集成功率放大器，实现多模和多频带操作。 偏移点包括例如增益和饱和点，频率响应，线性度和EVM。 具有以新颖配置布置的初级和次级绕组的集成多抽头变压器提供了由各个子放大器产生的功率的有效功率组合和传输到天线。

    Fast automatic gain control
    49.
    发明授权
    Fast automatic gain control 有权
    快速自动增益控制

    公开(公告)号：US08938036B2

    公开(公告)日：2015-01-20

    申请号：US13360817

    申请日：2012-01-30

    Applicant: Ariel Feldman ,  Udi Suissa

    Inventor： Ariel Feldman ,  Udi Suissa

    IPC: H04L27/08

    CPC classification number: H03G3/3068

    Abstract: A device and method of fast automatic gain control in quadrature receivers are disclosed. The AGC activity between the I and Q branches is split where in one branch the receive chain is in a certain gain state and in the other branch the receive chain is in another possible gain state, resulting in a significant shortening of the AGC duration of any IQ receiver.

    Abstract translation: 公开了正交接收机中快速自动增益控制的装置和方法。 I和Q分支之间的AGC活动被分裂，其中在一个分支中接收链处于一定的增益状态，而在另一个分支中，接收链处于另一个可能的增益状态，导致任意的AGC持续时间的显着缩短 IQ接收器

    Device and method for direct mixing of pulse density modulation (PDM) signals
    50.
    发明授权
    Device and method for direct mixing of pulse density modulation (PDM) signals 有权
    用于直接混合脉冲密度调制（PDM）信号的装置和方法

    公开(公告)号：US08937515B2

    公开(公告)日：2015-01-20

    申请号：US14060626

    申请日：2013-10-23

    Applicant: Moshe Haiut

    Inventor： Moshe Haiut

    IPC: H03K7/08 ,  H03M1/00

    CPC classification number: H03M1/00 ,  H04R3/005

    Abstract: A device for mixing multiple (N) pulse density modulated (PDM) bit streams of a bit rate, the device comprises an input logic, an error accumulation circuit, an error correction circuit and an adder of more than N bits; wherein the device is arranged to output an output PDM bit stream that represents a mixture of the multiple input PDM bit streams; wherein the output PDM bit stream comprises a plurality of output PDM bits, wherein a certain output PDM bit of a plurality of output PDM bits that form the output PDM bit stream is generated during a certain clock cycle; wherein the input logic is arranged to select, during each fraction of the certain clock cycle, a current bit of a selected PDM bit stream, wherein different PDM bit streams are selected during different fragments of the certain clock cycle; wherein the error accumulation circuit is arranged to store intermediate values during a first fraction till a penultimate fraction of the certain clock signal and to store a last value during a last fraction of the certain clock signal.

    Abstract translation: 一种用于混合比特率的多个（N）个脉冲密度调制（PDM）比特流的装置，该装置包括输入逻辑，误差累积电路，纠错电路和大于N比特的加法器; 其中所述设备被布置为输出表示所述多个输入PDM比特流的混合的输出PDM比特流; 其中所述输出PDM位流包括多个输出PDM位，其中在特定时钟周期期间产生形成所述输出PDM位流的多个输出PDM位中的某个输出PDM位; 其中所述输入逻辑被布置为在所述特定时钟周期的每个分数期间选择所选择的PDM比特流的当前比特，其中在所述特定时钟周期的不同片段期间选择不同的PDM比特流; 其中所述误差累积电路被布置为在第一分数期间存储中间值直到所述特定时钟信号的倒数第二分数，并且在所述特定时钟信号的最后部分期间存储最后一个值。

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