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    Microelectronic mechanical system and methods
    41.
    发明授权
    Microelectronic mechanical system and methods 有权
    微电子机械系统及方法

    公开(公告)号：US07183637B2

    公开(公告)日：2007-02-27

    申请号：US11129541

    申请日：2005-05-13

    Applicant: Mike Bruner

    Inventor： Mike Bruner

    IPC: H01L21/00 ,  H01L21/461

    CPC classification number: B81C1/00484 ,  B81B2201/0271 ,  B81B2203/0136 ,  B81C1/00246 ,  B81C1/00333 ,  B81C2201/0109 ,  B81C2201/014 ,  B81C2203/0136 ,  B81C2203/0735

    Abstract: The current invention provides for encapsulated release structures, intermediates thereof and methods for their fabrication. The multi-layer structure has a capping layer, that preferably comprises silicon oxide and/or silicon nitride, and which is formed over an etch resistant substrate. A patterned device layer, preferably comprising silicon nitride, is embedded in a sacrificial material, preferably comprising polysilicon, and is disposed between the etch resistant substrate and the capping layer. Access trenches or holes are formed in to capping layer and the sacrificial material are selectively etched through the access trenches, such that portions of the device layer are release from sacrificial material. The etchant preferably comprises a noble gas fluoride NGF2x (wherein Ng=Xe, Kr or Ar: and where x=1, 2 or 3). After etching that sacrificial material, the access trenches are sealed to encapsulate released portions the device layer between the etch resistant substrate and the capping layer. The current invention is particularly useful for fabricating MEMS devices, multiple cavity devices and devices with multiple release features.

    Abstract translation: 本发明提供了包封的释放结构，其中间体及其制备方法。 多层结构具有覆盖层，其优选地包括氧化硅和/或氮化硅，并且其形成在耐蚀刻衬底上。 优选地包括氮化硅的图案化器件层嵌入牺牲材料中，优选地包括多晶硅，并且设置在耐蚀刻衬底和覆盖层之间。 进入沟槽或孔形成在覆盖层中，并且牺牲材料通过进入沟槽被选择性地蚀刻，使得器件层的部分从牺牲材料释放。 蚀刻剂优选包含惰性气体氟化物NGF 2X（其中Ng = Xe，Kr或Ar：其中x = 1,2或3）。 在蚀刻该牺牲材料之后，进入沟槽被密封以将器件层的释放部分封装在耐蚀刻衬底和覆盖层之间。 本发明对于制造具有多个释放特征的MEMS器件，多腔器件和器件特别有用。

    Physical quantity sensor and method for manufacturing the same
    43.
    发明申请
    Physical quantity sensor and method for manufacturing the same 有权
    物理量传感器及其制造方法

    公开(公告)号：US20060008935A1

    公开(公告)日：2006-01-12

    申请号：US11169583

    申请日：2005-06-30

    Applicant: Makoto Asai

    Inventor： Makoto Asai

    IPC: H01L21/306 ,  G01P15/125

    CPC classification number: B81C1/00626 ,  B81B2201/0235 ,  B81B2201/0292 ,  B81B2203/0118 ,  B81C2201/014 ,  B81C2201/019 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0814

    Abstract: A physical quantity sensor includes: a semiconductor substrate; a cavity disposed in the substrate and extending in a horizontal direction of the substrate; a groove disposed on the substrate and reaching the cavity; a movable portion separated by the cavity and the groove so that the movable portion is movably supported on the substrate; and an insulation layer disposed on a bottom of the movable portion so that the insulation layer provides a roof of the cavity.

    Abstract translation: 物理量传感器包括：半导体衬底; 设置在所述基板中并在所述基板的水平方向上延伸的空腔; 设置在所述基板上并到达所述空腔的凹槽; 可移动部分，由空腔和沟槽分隔开，使得可移动部分可移动地支撑在基板上; 以及设置在所述可动部分的底部上的绝缘层，使得所述绝缘层提供所述空腔的顶部。

    Semiconductor device and method of producing the same
    47.
    发明申请
    Semiconductor device and method of producing the same 审中-公开
    半导体装置及其制造方法

    公开(公告)号：US20040104454A1

    公开(公告)日：2004-06-03

    申请号：US10605585

    申请日：2003-10-10

    Applicant: ROHM CO., LTD.

    Inventor： Masaki Takaoka ,  Noriyuki Shimoji

    IPC: H01L029/40

    CPC classification number: B81B3/007 ,  B81B2201/052 ,  B81B2203/0315 ,  B81B2203/0353 ,  B81C2201/014 ,  B81C2201/019 ,  H01L23/481 ,  H01L29/0657 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

    Abstract: A semiconductor device is disclosed which can be miniaturized and in which structures on a semiconductor substrate therein are difficult to delaminate, as well as a method of producing the same. The semiconductor device includes a semiconductor substrate main unit, and a thin portion that is thinner than the main unit and formed such that a recessed portion is formed in the semiconductor substrate and has at least one through hole formed therein. The thin portion is formed such that the etching rate of the thin portion is slower than the etching rate of the main unit. The thin portion provides a bridging structure between both sides of the recessed portion, and can mechanically and structurally strengthen the semiconductor device with respect to forces applied from the side surfaces of the main unit of the semiconductor substrate. Thus, structures such as wires, films, and semiconductor elements formed on the main unit and/or the thin portion of the semiconductor substrate or via the through holes will be difficult to detach from the semiconductor device.

    Abstract translation: 公开了可以小型化并且其中的半导体衬底上的结构难以分层的半导体器件及其制造方法。 半导体器件包括半导体衬底主单元和比主单元薄的薄部分，并且形成为在半导体衬底中形成凹部并且在其中形成有至少一个通孔。 薄部形成为使得薄部的蚀刻速度比主体的蚀刻速度慢。 薄壁部分在凹部的两侧之间提供桥接结构，并且可相对于从半导体衬底的主单元的侧表面施加的力来机械地和结构地加强半导体器件。 因此，形成在半导体基板的主单元和/或薄壁部分上或通过通孔的诸如导线，膜和半导体元件的结构将难以从半导体器件分离。

    Electronic device and method for fabricating the electronic device
    48.
    发明申请
    Electronic device and method for fabricating the electronic device 有权
    用于制造电子装置的电子装置和方法

    公开(公告)号：US20040053435A1

    公开(公告)日：2004-03-18

    申请号：US10601470

    申请日：2003-06-23

    Applicant: Matsushita Electric Industrial Co., Ltd.

    Inventor： Kimiya Ikushima ,  Hiroyoshi Komobuchi ,  Mikiya Uchida

    IPC: H01L021/00

    CPC classification number: G01J5/20 ,  B81B3/0072 ,  B81B2201/0207 ,  B81B2203/0127 ,  B81C1/00047 ,  B81C1/00801 ,  B81C2201/0109 ,  B81C2201/014 ,  G01F1/6845 ,  G01J5/023 ,  G01J5/024 ,  G01J5/045 ,  G01J5/10 ,  G01J5/34

    Abstract: A method for fabricating an electronic device includes the steps of: preparing a cavity defining sacrificial layer, at least the upper surface of which is covered with an etch stop layer; forming at least one first opening in the etch stop layer, thereby partially exposing the surface of the cavity defining sacrificial layer; etching the cavity defining sacrificial layer through the first opening, thereby defining a provisional cavity under the etch stop layer and a supporting portion that supports the etch stop layer thereon; and etching away a portion of the etch stop layer, thereby defining at least one second opening that reaches the provisional cavity through the etch stop layer and expanding the provisional cavity into a final cavity.

    Abstract translation: 一种制造电子器件的方法包括以下步骤：制备限定牺牲层的空腔，其至少其上表面被蚀刻停止层覆盖; 在蚀刻停止层中形成至少一个第一开口，从而部分地暴露限定牺牲层的空腔的表面; 蚀刻通过所述第一开口限定牺牲层的所述腔，从而在所述蚀刻停止层下方限定临时空腔，以及在其上支撑所述蚀刻停止层的支撑部分; 并且蚀刻掉蚀刻停止层的一部分，从而限定通过蚀刻停止层到达临时腔的至少一个第二开口，并将临时空腔膨胀成最终空腔。

    Micromechanical system fabrication method using (111) single crystalline silicon
    49.
    发明授权
    Micromechanical system fabrication method using (111) single crystalline silicon 有权
    （111）单晶硅的微机械系统制造方法

    公开(公告)号：US06689694B1

    公开(公告)日：2004-02-10

    申请号：US09715446

    申请日：2000-11-17

    Applicant: Dong-Il Cho ,  Sangwoo Lee ,  Sangjun Park

    Inventor： Dong-Il Cho ,  Sangwoo Lee ,  Sangjun Park

    IPC: H01L21311

    CPC classification number: C30B29/06 ,  B81B2203/0109 ,  B81B2203/0118 ,  B81C1/00801 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/014 ,  C30B33/00

    Abstract: Disclosed is a micromechanical system fabrication method using (111) single crystalline silicon as a silicon substrate and employing a reactive ion etching process in order to pattern a microstructure that will be separated from the silicon substrate and a selective release-etching process utilizing an aqueous alkaline solution in order to separate the microstructure from the silicon substrate. According to the micromechanical system fabrication method of the present invention, the side surfaces of microstructures can be formed to be vertical by employing the RIE technique. Furthermore, the microstructures can be readily separated from the silicon substrate by employing the selective release-etching technique using slow etching {111} planes as the etch stop in an aqueous alkaline solution. In addition, etched depths can be adjusted during the RIE step, thereby adjusting the thickness of the microstructure and the spacing between the microstructure and the silicon substrate.

    Abstract translation: 公开了一种使用（111）单晶硅作为硅衬底并采用反应离子蚀刻工艺以便将从硅衬底分离的微结构图案和利用碱性水溶液的选择性剥离蚀刻工艺的微机械系统制造方法 溶液以将微结构与硅衬底分离。 根据本发明的微机械系统制造方法，通过采用RIE技术，可以将微结构的侧面形成为垂直的。 此外，通过使用选择性剥离蚀刻技术，通过使用慢蚀刻{111}晶面作为碱性水溶液中的蚀刻停止，微结构可以容易地与硅衬底分离。 此外，可以在RIE步骤期间调整蚀刻深度，从而调整微结构的厚度和微结构与硅衬底之间的间隔。

    Silicon on insulator standoff and method for manufacture thereof
    50.
    发明申请
    Silicon on insulator standoff and method for manufacture thereof 审中-公开
    硅绝缘体间隔及其制造方法

    公开(公告)号：US20030197176A1

    公开(公告)日：2003-10-23

    申请号：US10128368

    申请日：2002-04-22

    Applicant: Glimmerglass Networks, Inc.

    Inventor： James P. Spallas ,  Andres Fernandez ,  Thomas DeBey ,  Lawrence P. Muray

    IPC: H01L029/04

    CPC classification number: B81C1/00119 ,  B81B2201/042 ,  B81C2201/0104 ,  B81C2201/014 ,  B81C2201/017 ,  B81C2201/019

    Abstract: Method for fabricating ultrathin gaps producing ultrashort standoffs in array structures includes sandwiching a patterned device layer between a silicon standoff layer and a silicon support layer, providing that the back surfaces of the respective silicon support layer and the standoff layer are polished to a desired thickness corresponding to the desired standoff height on one side and to at least a minimum height for mechanical strength on the opposing side, as well as to a desired smoothness. Standoffs and mechanical supports are then fabricated by etching to produce voids with the dielectric oxides on both sides of the device layer serving as suitable etch stops. Thereafter, the exposed portions of the oxide layers are removed to release the pattern, and a package layer is mated with the standoff voids to produce a finished device. The standoff layer can be fabricated to counteract curvature.

    Abstract translation: 用于制造在阵列结构中产生超短距离的超薄间隙的方法包括在硅隔离层和硅支撑层之间夹着图案化的器件层，条件是相应的硅支撑层和支座层的背面被抛光到相应的所需厚度 达到一侧上所需的间隔高度，并且至少在相对侧上的机械强度的最小高度以及期望的平滑度。 然后通过蚀刻制造支座和机械支撑件以产生空隙，其中装置层两侧的电介质氧化物用作合适的蚀刻停止点。 此后，去除氧化物层的暴露部分以释放图案，并且将封装层与间隙空隙配合以产生成品装置。 可以制造隔离层以抵消曲率。

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