公开(公告)号：US07052622B2

公开(公告)日：2006-05-30

申请号：US10265620

申请日：2002-10-08

Applicant: Jeffrey D. Chinn ,  Robert Z. Bachrach

Inventor： Jeffrey D. Chinn ,  Robert Z. Bachrach

IPC: C03C15/00

CPC classification number: B81C1/00476 ,  B81C99/0065 ,  B81C2201/0142

Abstract: A method of determining the time to release of a movable feature in a multilayer substrate of silicon-containing materials including alternate layers of polysilicon and silicon oxide wherein a mass monitoring device determines the mass of a released feature, and the substrate is etched with anhydrous hydrogen fluoride until the substrate mass is equivalent to that of the released movable feature when the etch time is noted. A suitable mass monitoring device is a quartz crystal microbalance.

公开(公告)号：US20060027532A1

公开(公告)日：2006-02-09

申请号：US10524525

申请日：2003-08-14

Applicant: Martin Hausner

Inventor： Martin Hausner

IPC: B44C1/22

CPC classification number: H01L21/3065 ,  B81C1/00626 ,  B81C2201/0132 ,  B81C2201/0142 ,  H01L21/30655 ,  H01L21/3081

Abstract: A method for the selective removal of material from a substrate surface for forming a deepening comprises the steps of applying a mask onto the substrate surface in accordance with the desired selective removal and dry-etching the substrate, a metal, preferably aluminum, being used as the masking material. Power may be coupled inductively to a plasma.

Abstract translation: 用于从衬底表面选择性去除形成深化的材料的方法包括以下步骤：根据所需的选择性去除和干蚀刻衬底，金属，优选铝，将掩模施加到衬底表面上，其用作 掩蔽材料。 功率可以感应耦合到等离子体。

公开(公告)号：US06891650B2

公开(公告)日：2005-05-10

申请号：US10755339

申请日：2004-01-13

Applicant: Yoshihiro Mizuno ,  Satoshi Ueda ,  Osamu Tsuboi ,  Ippei Sawaki ,  Hisao Okuda ,  Fumio Yamagishi ,  Norinao Kouma

Inventor： Yoshihiro Mizuno ,  Satoshi Ueda ,  Osamu Tsuboi ,  Ippei Sawaki ,  Hisao Okuda ,  Fumio Yamagishi ,  Norinao Kouma

IPC: B01D53/88 ,  B01J8/04 ,  B81B3/00 ,  B81C1/00 ,  C01B3/16 ,  G02B26/08

CPC classification number: G02B26/0841 ,  B01D53/885 ,  B01J8/0453 ,  B01J8/0496 ,  B01J2208/00212 ,  B01J2208/00309 ,  B01J2208/025 ,  B81B2201/045 ,  B81B2203/0136 ,  B81C1/00142 ,  B81C1/00626 ,  B81C2201/0142 ,  C01B3/16 ,  C01B2203/0288 ,  C01B2203/045 ,  C01B2203/0485 ,  Y10S359/904

Abstract: A method of making a micromirror unit is provided. In accordance with the method, a micromirror unit is made from a material substrate having a multi-layer structure composed of silicon layers and at least one intermediate layer. The resulting micromirror unit includes a mirror forming base, a frame and a torsion bar. The method includes the following steps. First, a pre-torsion bar is formed by subjecting one of the silicon layers to etching. The obtained pre-torsion bar is rendered smaller in thickness than the mirror forming base and is held in contact with the intermediate layer. Then, the desired torsion bar is obtained by removing the intermediate layer contacting with the pre-torsion bar.

Abstract translation: 提供了制造微镜单元的方法。 根据该方法，微镜单元由具有由硅层和至少一个中间层构成的多层结构的材料基板制成。 所得到的微镜单元包括反射镜形成基座，框架和扭杆。 该方法包括以下步骤。 首先，通过使一个硅层进行蚀刻来形成预扭杆。 所获得的预扭杆的厚度比反射镜形成基座的厚度小，并与中间层保持接触。 然后，通过去除与预扭杆接触的中间层来获得所需的扭力杆。

公开(公告)号：US06852560B2

公开(公告)日：2005-02-08

申请号：US10853943

申请日：2004-05-26

Applicant: Thomas N. Corso

Inventor： Thomas N. Corso

IPC: B81B1/00 ,  H01L21/00 ,  H01L21/301 ,  H01L21/302 ,  H01L21/46 ,  H01L21/78

CPC classification number: B81C1/00087 ,  B81B2201/058 ,  B81C2201/0142

Abstract: A method for fabricating a nozzle of microchip-based electrospray device is disclosed. The method includes using a primary mask to accurately define the nozzle feature including the annulus and the through hole of the electrospray device. A secondary masking step is conducted to pattern the through channel (typical the photoresist would serve as the secondary mask), followed by the defining and etching of the primary mask containing the full nozzle feature. The secondary mask serves to selectively mask given areas of the primary mask for subsequent etching. The through hole feature of the secondary mask aligns over the already patterned primary mask through channel, except that the secondary mask contains a slightly larger through channel diameter. This serves to mask off the annulus, but allowing the silicon through channel to be exposed for etching.

Abstract translation: 公开了一种用于制造基于微芯片的电喷雾装置的喷嘴的方法。 该方法包括使用主掩模来精确地限定包括电喷雾装置的环形部分和通孔的喷嘴特征。 进行二次掩模步骤以对穿通通道进行图案化（典型地，光致抗蚀剂将用作辅助掩模），然后限定和蚀刻含有全喷嘴特征的主掩模。 辅助掩模用于选择性地掩蔽初级掩模的给定区域用于随后的蚀刻。 辅助掩模的通孔特征通过通道对准已经图案化的初级掩模，不同之处在于次要掩模包含稍大的通道直径。 这用于掩盖环形，但允许硅通过沟道暴露以进行蚀刻。

公开(公告)号：US20040219705A1

公开(公告)日：2004-11-04

申请号：US10853943

申请日：2004-05-26

Inventor： Thomas N. Corso

IPC: H01L021/00 ,  H01L021/301 ,  H01L021/46 ,  H01L021/78

CPC classification number: B81C1/00087 ,  B81B2201/058 ,  B81C2201/0142

Abstract: A method for fabricating a nozzle of microchip-based electrospray device is disclosed. The method includes using a primary mask to accurately define the nozzle feature including the annulus and the through hole of the electrospray device. A secondary masking step is conducted to pattern the through channel (typical the photoresist would serve as the secondary mask), followed by the defining and etching of the primary mask containing the full nozzle feature. The secondary mask serves to selectively mask given areas of the primary mask for subsequent etching. The through hole feature of the secondary mask aligns over the already patterned primary mask through channel, except that the secondary mask contains a slightly larger through channel diameter. This serves to mask off the annulus, but allowing the silicon through channel to be exposed for etching.

Abstract translation: 公开了一种用于制造基于微芯片的电喷雾装置的喷嘴的方法。 该方法包括使用主掩模来精确地限定包括电喷雾装置的环形部分和通孔的喷嘴特征。 进行二次掩模步骤以对穿通通道进行图案化（典型地，光致抗蚀剂将用作辅助掩模），然后限定和蚀刻含有全喷嘴特征的主掩模。 辅助掩模用于选择性地掩蔽初级掩模的给定区域用于随后的蚀刻。 辅助掩模的通孔特征通过通道对准已经图案化的初级掩模，不同之处在于次要掩模包含稍大的通道直径。 这用于掩盖环形，但允许硅通过沟道暴露以进行蚀刻。

公开(公告)号：US20030228759A1

公开(公告)日：2003-12-11

申请号：US10410254

申请日：2003-04-10

Inventor： Shinichi Uehara ,  Yuko Sato ,  Ken Sumiyoshi ,  Setsuo Kaneko ,  Jin Matsushima

IPC: H01L021/302 ,  H01L021/461

CPC classification number: G02B3/0056 ,  B81B2207/056 ,  B81C1/00031 ,  B81C2201/0133 ,  B81C2201/0142 ,  C03C15/00 ,  C03C17/34 ,  C03C2204/08 ,  C03C2218/34 ,  G02B3/0012 ,  G02F1/133526 ,  Y10T428/131 ,  Y10T428/249969 ,  Y10T428/315

Abstract: In a formation method for forming a fine structure in a workpiece containing an etching control component, using an isotropic etching process, a mask having an opening is applied to the workpiece, and the workpiece is etched with an etching solution to thereby form a recess, corresponding to a shape of the opening, in a surface of the workpiece. The etching of the workpiece is stopped due to the etching control component eluted out of the workpiece in the etching solution within the recess during the isotropic etching process.

Abstract translation: 在包含蚀刻控制部件的工件中形成精细结构的形成方法中，使用各向同性蚀刻工序，将具有开口的掩模施加到工件上，用蚀刻溶液蚀刻工件，从而形成凹部， 对应于工件的表面中的开口的形状。 由于在各向同性蚀刻工艺期间蚀刻控制部件在凹陷内的蚀刻溶液中从工件中洗脱出来，停止了工件的蚀刻。

公开(公告)号：US06506620B1

公开(公告)日：2003-01-14

申请号：US09724515

申请日：2000-11-27

Applicant: Bruce R. Scharf ,  Joel A. Kubby ,  Chuang-Chia Lin ,  Alex T. Tran ,  Andrew J. Zosel ,  Peter M. Gulvin ,  Jingkuang Chen

Inventor： Bruce R. Scharf ,  Joel A. Kubby ,  Chuang-Chia Lin ,  Alex T. Tran ,  Andrew J. Zosel ,  Peter M. Gulvin ,  Jingkuang Chen

IPC: H01L2100

CPC classification number: B81C1/00484 ,  B81B2201/042 ,  B81B2203/0118 ,  B81C1/00666 ,  B81C2201/0142

Abstract: The present invention provides a micromechanical or microoptomechanical structure produced by a process comprising defining the structure in a single-crystal silicon layer separated by an insulator layer from a substrate layer; selectively etching the single crystal silicon layer; depositing and etching a polysilicon layer on the insulator layer, with remaining polysilicon forming mechanical elements of the structure; metalizing a backside of the structure; and releasing the formed structure.

Abstract translation: 本发明提供了一种微机械或微机电结构，其通过包括限定由绝缘体层与衬底层分隔的单晶硅层中的结构的方法而产生; 选择性地蚀刻单晶硅层; 沉积和蚀刻绝缘体层上的多晶硅层，剩余的多晶硅形成结构的机械元件; 金属化结构的背面; 并释放形成的结构。

公开(公告)号：US20240174512A1

公开(公告)日：2024-05-30

申请号：US17994471

申请日：2022-11-28

Applicant: TAIWAN MASK CORPORATION

Inventor： SHANG-KUANG WU ,  YU-TSUNG FU ,  MING-WEI HUANG

IPC: B81C1/00

CPC classification number: B81C1/00055 ,  B81C2201/0133 ,  B81C2201/0142 ,  B81C2201/0159

Abstract: A MEMS probe and manufacturing method thereof are provided. The method is mainly to form connected first-level, second-level, and third-level pin grooves on both sides of the silicon substrate through an etching process, followed by two electroplating processes to deposit nickel-cobalt-phosphorus alloy in the first-level pin groove to form the tip of the microprobe, and to deposit nickel-cobalt alloy in the second-level pin groove and the third-level pin to form the pin head and pin arm, thereby forming a three-level microprobe. A circuit substrate made of ceramic material is disposed with at least one window, the surface of the circuit substrate adjacent to the window is provided with a plurality of circuit pads, and the circuit substrate is abutted to the pin arm of the microprobe. The silicon substrate is then removed, to form a plurality of cantilever microprobes made of nickel-cobalt-phosphorus alloy and nickel-cobalt alloy on the circuit substrate.

公开(公告)号：US20190198345A1

公开(公告)日：2019-06-27

申请号：US16289428

申请日：2019-02-28

Applicant: Lam Research Corporation

Inventor： Andreas Fischer ,  Thorsten Lill ,  Richard Janek ,  John Boniface

IPC: H01L21/311 ,  H01J37/32 ,  C23F4/00 ,  C23F1/12 ,  C23F1/00 ,  C23C16/02 ,  H01L21/3065 ,  H01L21/3213

CPC classification number: H01L21/31122 ,  B81C2201/0135 ,  B81C2201/0142 ,  C23C16/0245 ,  C23F1/00 ,  C23F1/12 ,  C23F4/00 ,  H01J37/32009 ,  H01J37/32082 ,  H01J2237/334 ,  H01L21/30655 ,  H01L21/32136

Abstract: A method for performing atomic layer etching (ALE) on a substrate, including the following method operations: performing a surface modification operation on a surface of the substrate, the surface modification operation configured to convert at least one monolayer of the substrate surface to a modified layer; performing a removal operation on the substrate surface, to remove the modified layer from the substrate surface, wherein removing the modified layer includes exposing the substrate surface to a metal complex, such that a ligand exchange reaction occurs between the metal complex and converted species of the modified layer; performing, following the removal operation, a plasma treatment on the substrate surface, the plasma treatment configured to remove residues formed from the exposure of the substrate surface to the metal complex, wherein the residues are volatilized by the plasma treatment; repeating the foregoing operations until a predefined thickness has been etched from the substrate surface.

公开(公告)号：US20190023563A1

公开(公告)日：2019-01-24

申请号：US15757672

申请日：2016-09-09

Applicant: DENSO CORPORATION

Inventor： Akira OGAWA ,  Yoshitaka NODA ,  Tetsuo YOSHIOKA ,  Yuhei SHIMIZU

IPC: B81C1/00

CPC classification number: B81C1/00579 ,  B81B2201/033 ,  B81C2201/0112 ,  B81C2201/0132 ,  B81C2201/0139 ,  B81C2201/0142 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0814 ,  G01P2015/0882

Abstract: A semiconductor device production method includes performing trench etching to form a trench in a thickness direction of a semiconductor layer so that both of a first pattern portion and a second pattern portion whose side walls face each other across the trench are formed. In the trench etching, the semiconductor layer is etched and removed while a protective film is formed on a surface of the semiconductor layer, and the trench etching is performed so that the first pattern portion and the second pattern portion are configured to have a same potential or a same temperature during the trench etching.