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公开(公告)号:US12080210B2
公开(公告)日:2024-09-03
申请号:US18102783
申请日:2023-01-30
IPC分类号: G09G3/20
CPC分类号: G09G3/20 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2320/0233 , G09G2330/021
摘要: The application provides a display panel, integrated chip component and display device. The display panel includes: a first display area and a second display area; pixel circuits comprising first pixel circuits and second pixel circuits, the first pixel circuits and the second pixel circuits being configured to provide driving currents for light-emitting elements in the first display area and the second display area, respectively; and first pixel units and second pixel units, each first pixel unit comprising a first pixel circuit and a light-emitting element connected to the first pixel circuit, and each second pixel unit comprising a second pixel circuit and a light-emitting element connected to the second pixel circuit; wherein each first pixel unit is configured to receive a first power supply signal V1 and a second power supply signal V2, V1>V2.
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公开(公告)号:US12073806B2
公开(公告)日:2024-08-27
申请号:US17134770
申请日:2020-12-28
IPC分类号: G09G3/36 , G06F1/3234 , G06F12/0811 , G06F12/0895 , G09G3/20
CPC分类号: G09G3/3618 , G06F1/3265 , G06F12/0811 , G06F12/0895 , G09G3/2092 , G09G2330/021
摘要: Refreshing displays using on-die cache, including: determining that a static display condition has been met; storing, in cache memory of a processor, first display data; and displaying the first display data from the cache memory.
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公开(公告)号:US20240282266A1
公开(公告)日:2024-08-22
申请号:US18023712
申请日:2022-01-14
发明人: Miao LIU , Xing YAO , Yipeng CHEN , Teng CHEN
IPC分类号: G09G3/3266
CPC分类号: G09G3/3266 , G09G2310/08 , G09G2330/021
摘要: Disclosed is a drive control circuit including an input circuit (10), a first output circuit (11), and a second output circuit (12). The first output circuit (11) is electrically connected with the input circuit (10) and a first output end (OUT1) and is configured to output a first output signal from the first output end (OUT1) under control of the input circuit (11). The second output circuit (12) is electrically connected with the input circuit (10) and a second output end (OUT2), or electrically connected with the first output end (OUT1) and a second output end (OUT2), and is configured to output a second output signal from the second output end (OUT2) under control of the input circuit (10) or the first output end (OUT1). The first output signal is different from the second output signal.
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公开(公告)号:US20240282244A1
公开(公告)日:2024-08-22
申请号:US18388835
申请日:2023-11-11
发明人: Yoosung KIM , Hyunho LIM
IPC分类号: G09G3/32
CPC分类号: G09G3/32 , G09G2310/027 , G09G2320/0276 , G09G2330/021
摘要: A display apparatus includes: a gamma reference voltage generator, a digital-to-analog converter, an amplifier and a bias voltage applier. The gamma reference voltage generator is configured to generate a gamma reference voltage. The digital-to-analog converter is configured to convert a data signal to a data voltage based on the gamma reference voltage. The amplifier is configured to receive the data voltage from the digital-to-analog converter and to output the data voltage to a data line. The bias voltage applier is configured to output a first bias voltage to the gamma reference voltage generator and to output a second bias voltage to the amplifier. The bias voltage applier is turned off while input image data have a black image.
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公开(公告)号:US20240282231A1
公开(公告)日:2024-08-22
申请号:US18172291
申请日:2023-02-21
发明人: Chieh-An Lin , Keko-Chun Liang , Jhih-Siou Cheng
CPC分类号: G09G3/20 , H02J7/345 , G09G2310/0202 , G09G2310/0248 , G09G2310/027 , G09G2310/0289 , G09G2310/0291 , G09G2330/021
摘要: A display driver and a charge recycling method are provided. The display driver includes a charging and discharging circuit and a control circuit. A first terminal of the charging and discharging circuit is coupled to at least one of the scan lines, and a second terminal of the charging and discharging circuit is coupled to at least one of the data lines. The control circuit is coupled to a first control terminal and a second control terminal of the charging and discharging circuit. The charging and discharging circuit receives a first current generated by discharging the at least one of the scan lines to charge the capacitor based on a first control signal. The charging and discharging circuit discharges the capacitor to generate a second current for charging the at least one of the data lines based on a second control signal.
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公开(公告)号:US20240280869A1
公开(公告)日:2024-08-22
申请号:US18645658
申请日:2024-04-25
发明人: Atsushi Umezaki
IPC分类号: G02F1/1362 , G02F1/133 , G02F1/1335 , G02F1/1337 , G02F1/1345 , G02F1/1368 , G02F1/139 , G09G3/34 , G09G3/36 , G11C19/28 , H01L21/67 , H01L27/06 , H01L27/12 , H01L27/15 , H01L29/24 , H01L29/786 , H10K50/842 , H10K59/121 , H10K59/123 , H10K59/124 , H10K59/131 , H10K59/35 , H10K71/00 , H10K102/00
CPC分类号: G02F1/136286 , G02F1/13306 , G02F1/13452 , G02F1/136213 , G02F1/1368 , G09G3/342 , G09G3/3674 , G09G3/3677 , G09G3/3685 , G11C19/28 , H01L27/06 , H01L27/1222 , H01L27/1225 , H01L27/124 , H01L27/1255 , H01L27/15 , H01L27/156 , H01L29/247 , H01L29/78693 , G02F1/133622 , G02F1/133753 , G02F1/1393 , G02F2202/103 , G09G3/3655 , G09G2300/0426 , G09G2300/0452 , G09G2310/024 , G09G2310/0286 , G09G2310/08 , G09G2320/0252 , G09G2330/021 , H01L21/67167 , H10K50/8426 , H10K59/1213 , H10K59/1216 , H10K59/123 , H10K59/124 , H10K59/131 , H10K59/35 , H10K59/351 , H10K59/352 , H10K71/00 , H10K2102/3023 , H10K2102/3026 , H10K2102/3031
摘要: A first transistor, a second transistor, a third transistor, a fourth transistor are provided. In the first transistor, a first terminal is electrically connected to a first wiring; a second terminal is electrically connected to a gate terminal of the second transistor; a gate terminal is electrically connected to a fifth wiring. In the second transistor, a first terminal is electrically connected to a third wiring; a second terminal is electrically connected to a sixth wiring. In the third transistor, a first terminal is electrically connected to a second wiring; a second terminal is electrically connected to the gate terminal of the second transistor; a gate terminal is electrically connected to a fourth wiring. In the fourth transistor, a first terminal is electrically connected to the second wiring; a second terminal is electrically connected to the sixth wiring; a gate terminal is connected to the fourth wiring.
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公开(公告)号:US20240280849A1
公开(公告)日:2024-08-22
申请号:US18654191
申请日:2024-05-03
发明人: William Dunn
IPC分类号: G02F1/1333 , G01C9/06 , G04G9/00 , G04G21/02 , G09G3/34
CPC分类号: G02F1/133382 , G01C9/06 , G04G9/0064 , G04G21/02 , G09G3/3406 , G09G2320/041 , G09G2330/021
摘要: Digital signage unit, such as for digital out of home advertising, with monitoring features are provided. The digital signage unit include an electronic display, an orientation detection device, and a controller which receives orientation data from the orientation detection device and determines, on an ongoing basis, an orientation of the display unit based, at least in part, from the orientation data.
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公开(公告)号:US12067938B2
公开(公告)日:2024-08-20
申请号:US17622785
申请日:2021-12-17
IPC分类号: G09G3/3233
CPC分类号: G09G3/3233 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2310/08 , G09G2330/021
摘要: A pixel circuit, a display device, and a method of driving the same are provided. The pixel circuit includes a light emitting element, a first transistor, and a second transistor. In response to a time voltage signal provided by a time voltage line RST, the second transistor T2 is turned off during a display scan period of one frame period and is turned on during a self scan period of one frame period to reset the first transistor T1 during the self scan period of one frame period.
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公开(公告)号:US12066634B2
公开(公告)日:2024-08-20
申请号:US18234989
申请日:2023-08-17
申请人: Snap Inc.
发明人: Robert Matthew Bates , Ilteris Canberk , Brandon Carrillo , David G. Fliszar , Adam Douglas Greengard , Kenneth Kubala , David Meisenholder , Jonathan M Rodriguez, II , Amit Singh , Samuel Thompson
IPC分类号: G02B27/01 , G06T11/60 , G09G3/32 , H04B1/3827
CPC分类号: G02B27/0172 , G02B27/0176 , G02B27/0179 , G06T11/60 , G09G3/32 , H04B1/385 , G02B2027/0112 , G02B2027/0138 , G02B2027/014 , G02B2027/0178 , G02B2027/0187 , G09G2330/021 , G09G2354/00
摘要: The present application discloses examples of various apparatuses and systems that can be utilized for augmented reality. According to one example, a wearable device that can optionally comprise: a frame configured for wearing by a user; one or more optical elements mounted on the frame; an array having a plurality of light emitting diodes coupled to the one or more optical elements, wherein the one or more optical elements and the array are mounted within a field of view of the user when the frame is worn by the user; and additional onboard electronic components carried by the frame including at least a battery that is configured to provide for electrically powered operation of the array.
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公开(公告)号:US20240274090A1
公开(公告)日:2024-08-15
申请号:US18566949
申请日:2021-07-05
发明人: Kaoru YAMAMOTO
IPC分类号: G09G3/3275 , G09G3/3266
CPC分类号: G09G3/3275 , G09G3/3266 , G09G2300/043 , G09G2310/0278 , G09G2310/0286 , G09G2310/08 , G09G2330/021
摘要: To realize frame narrowing of a display device that uses a display element driven by a current. A second scanning signal line drive circuit configured to drive second scanning signal lines each connected to a control terminal of a writing control transistor is constituted by a shift register composed of unit circuits equal in number to half a number of the second scanning signal lines. Each of the unit circuits included in the shift register collectively drives two of the second scanning signal lines adjacent to each other. In a period during which a power supply control transistor and a light emission control transistor are maintained in an off state and the writing control transistor is maintained in an on state in first and second pixel circuits connected to the two second scanning signal lines adjacent to each other, a threshold voltage compensation transistor and an initialization transistor in the first pixel circuit and a threshold voltage compensation transistor and an initialization transistor in the second pixel circuit are sequentially set to an on state for a predetermined period each.
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