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    Clock synchronized non-volatile memory device
    43.
    发明授权
    Clock synchronized non-volatile memory device 有权
    时钟同步非易失性存储器件

    公开(公告)号：US06747941B2

    公开(公告)日：2004-06-08

    申请号：US10373751

    申请日：2003-02-27

    Applicant: Hitoshi Miwa ,  Hiroaki Kotani

    Inventor： Hitoshi Miwa ,  Hiroaki Kotani

    IPC: G11C1134

    CPC classification number: G11C16/32 ,  G11C7/1006 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3431 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C2211/5643 ,  G11C2211/5647 ,  G11C2211/565

    Abstract: A non volatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, plural nonvolatile memory cells, and first and second volatile memories. The clock and command terminals respectively receive a first clock signal and commands including read and program commands. In response to the read command, the control circuit controls reading data from the memory cells, stores read data to the second volatile memory, transfers data to first volatile memory, and outputs data via the other terminal except the command terminal in response to the first clock signal. In response to the program command, the control circuit controls receiving data via the other terminal except the command terminal in response to the first clock signal, stores received data to the first volatile memory, transfers data to the second volatile memory, and writes data to the memory cells.

    Abstract translation: 一种非易失性存储装置，包括控制电路，具有时钟，命令和其他终端的多个终端，多个非易失性存储单元以及第一和第二易失性存储器。 时钟和命令终端分别接收第一时钟信号和包括读取和编程命令的命令。 响应于读取命令，控制电路控制从存储器单元读取数据，将读取的数据存储到第二易失性存储器，将数据传送到第一易失性存储器，并且响应于第一可变存储器，经由除命令终端之外的另一终端输出数据 时钟信号。 响应于程序命令，控制电路响应于第一时钟信号控制除了命令终端之外的另一终端的接收数据，将接收的数据存储到第一易失性存储器，将数据传送到第二易失性存储器，并将数据写入 记忆细胞。

    Non-volatile semiconductor memory
    45.
    发明申请
    Non-volatile semiconductor memory 有权
    非易失性半导体存储器

    公开(公告)号：US20040057310A1

    公开(公告)日：2004-03-25

    申请号：US10664977

    申请日：2003-09-22

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Koji Hosono ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Kenichi Imamiya

    IPC: G11C007/00

    CPC classification number: G11C16/0483 ,  G11C5/145 ,  G11C7/1006 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C2211/5643

    Abstract: A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has a first latch and a second latch that are selectively connected to the memory cell array and transfer data each other. A controller controls the reprogramming and retrieval circuits on data-reprogramming operation to and data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches in storing the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.

    Abstract translation: 非易失性半导体器件具有存储单元阵列，其具有电可擦除可编程非易失性存储器单元，重新编程和检索电路，其临时存储要存储在存储单元阵列中的要编程的数据并感测从存储器单元阵列检索的数据。 每个重新编程和检索电路具有选择性地连接到存储单元阵列并且彼此传送数据的第一锁存器和第二锁存器。 一个控制器控制重新编程和检索电路的数据重新编程操作和数据检索操作从存储单元阵列。 每个重新编程和检索电路都具有多级逻辑操作模式和缓存操作模式。 在多级逻辑操作模式中，使用第一和第二锁存器在存储单元之一中存储两位四电平数据来执行二位四电平数据的高位和低位的重新编程和检索 在预定的阈值电平范围内。 在高速缓存操作模式中，根据第一地址选择的存储器单元之一和第一锁存器之间的数据传输是在第二锁存器和输入/输出端子之间根据第二地址相对于 要存储在其中一个存储单元中的一位二电平数据。

    NONVOLATILE MEMORY DEVICE AND REFRESHING METHOD
    47.
    发明申请
    NONVOLATILE MEMORY DEVICE AND REFRESHING METHOD 失效
    非易失性存储器件和刷新方法

    公开(公告)号：US20030016557A1

    公开(公告)日：2003-01-23

    申请号：US10223370

    申请日：2002-08-20

    Inventor： Hitoshi Miwa ,  Hiroaki Kotani

    IPC: G11C011/34

    CPC classification number: G11C16/32 ,  G11C7/1006 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3431 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C2211/5643 ,  G11C2211/5647 ,  G11C2211/565

    Abstract: At the data programming time, data of a plurality of bits are transformed by a data transforming logic circuit into data (multi-value data) according to the combination of the bits, and the transformed data are sequentially transferred to a latch circuit connected to the bit lines of a memory array. A program pulse is generated according to the data latched in the latch circuit and is applied to a memory element of a selected state correspondingly to the multi-value data. At the data reading operation, the states of the memory elements are read out by changing the read voltage to intermediate values of the individual threshold values and are transferred to and latched in a register for storing the multi-value data, so that the original data may be restored by a data inverse transforming logic circuit on the basis of the multi-value data stored in the register. As a result, the peripheral circuit scale of the memory array can be suppressed to a relatively small size, and programming operation performed in a short time can be realized.

    Abstract translation: 在数据编程时，根据比特的组合，由数据变换逻辑电路将多个比特的数据变换为数据（多值数据），并将变换后的数据依次传送到与 存储器阵列的位线。 根据锁存在锁存电路中的数据产生编程脉冲，并将其应用于与多值数据对应的选择状态的存储元件。 在数据读取操作中，通过将读取的电压改变为各个阈值的中间值来读出存储元件的状态，并将其传送到并存储在用于存储多值数据的寄存器中，使得原始数据 可以通过基于存储在寄存器中的多值数据的数据逆变换逻辑电路来恢复。 结果，可以将存储器阵列的外围电路规模抑制到相对小的尺寸，并且可以实现在短时间内执行的编程操作。

    Nonvolatile memory device and refreshing method
    48.
    发明授权
    Nonvolatile memory device and refreshing method 有权
    非易失性存储器件和刷新方法

    公开(公告)号：US06366495B2

    公开(公告)日：2002-04-02

    申请号：US09817021

    申请日：2001-03-27

    Applicant: Hitoshi Miwa ,  Hiroaki Kotani

    Inventor： Hitoshi Miwa ,  Hiroaki Kotani

    IPC: G11C1134

    CPC classification number: G11C16/32 ,  G11C7/1006 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3431 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C2211/5643 ,  G11C2211/5647 ,  G11C2211/565

    Abstract: At the data programming, plural data bit is transformed by a data transforming logic circuit into multi-value data according to the combination of bits, and the transformed data are sequentially transferred to a latch circuit connected to bit lines of a memory array. A program pulse is generated according to the latched data and is applied to a memory element at a state corresponding to the multi-value data. During data reading, the states of the memory elements are read out by changing the read voltage to intermediate values of individual threshold values and latched in a register. The original data may be restored by a data inverse transforming logic circuit based on the multi-value data stored in the register.

    Abstract translation: 在数据编程中，根据比特的组合，将数据变换逻辑电路将多个数据位变换为多值数据，并将变换后的数据依次传送到与存储器阵列的位线连接的锁存电路。 根据锁存的数据产生编程脉冲，并以对应于多值数据的状态将其应用于存储元件。 在数据读取期间，通过将读取的电压改变为各个阈值的中间值并将其锁存在寄存器中来读出存储器元件的状态。 可以通过基于存储在寄存器中的多值数据的数据逆变换逻辑电路来恢复原始数据。

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