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41.发明公开公开(公告)号：US20240235571A9
公开(公告)日：2024-07-11
申请号：US18369816
申请日：2023-09-18
申请人： MEDIATEK INC.
发明人： Wenchang Huang
摘要： A multi-stage comparator includes a first stage circuit, a second stage circuit, and a control circuit. The first stage circuit receives an input signal of the multi-stage comparator, generates a first-stage output signal according to the input signal, and outputs the first-stage output signal at an output port of the first stage circuit. The second stage circuit receives a second-stage input signal at an input port of the second stage circuit, and performs a second-stage operation to generate an output signal of the multi-stage comparator. The control circuit is coupled between the output port of the first stage circuit and the input port of the second stage circuit, and controls a start time of the second-stage operation.
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42.发明公开公开(公告)号：US20240137039A1
公开(公告)日：2024-04-25
申请号：US18369816
申请日：2023-09-17
申请人： MEDIATEK INC.
发明人： Wenchang Huang
摘要： A multi-stage comparator includes a first stage circuit, a second stage circuit, and a control circuit. The first stage circuit receives an input signal of the multi-stage comparator, generates a first-stage output signal according to the input signal, and outputs the first-stage output signal at an output port of the first stage circuit. The second stage circuit receives a second-stage input signal at an input port of the second stage circuit, and performs a second-stage operation to generate an output signal of the multi-stage comparator. The control circuit is coupled between the output port of the first stage circuit and the input port of the second stage circuit, and controls a start time of the second-stage operation.
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43.发明公开公开(公告)号：US20240106453A1
公开(公告)日：2024-03-28
申请号：US18528968
申请日：2023-12-05
CPC分类号： H03M1/502 , H03K3/0315 , H03M1/1255
摘要： A transition-state output device includes: a ring oscillator circuit; a state machine changing in state according to a change in state of the ring oscillator circuit; a transition-state acquisition section acquiring and holding state information including a signal output from the ring oscillator circuit and a signal output from the state machine, synchronously with a reference signal; and an internal-state calculation section calculating an internal state corresponding to a number of changes in state of the ring oscillator circuit, based on the state information held by the transition-state acquisition section. A time until the internal state, after transitioning from a first internal state to a second internal state, transitions to the first internal state again is longer than a time interval of updating the state information held by the transition-state acquisition section.
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44.发明授权公开(公告)号：US11888499B2
公开(公告)日：2024-01-30
申请号：US17533373
申请日：2021-11-23
CPC分类号： H03M1/502 , H03K3/0315 , H03M1/1255
摘要： A transition-state output device includes: a ring oscillator circuit; a state machine changing in state according to a change in state of the ring oscillator circuit; a transition-state acquisition section acquiring and holding state information including a signal output from the ring oscillator circuit and a signal output from the state machine, synchronously with a reference signal; and an internal-state calculation section calculating an internal state corresponding to a number of changes in state of the ring oscillator circuit, based on the state information held by the transition-state acquisition section. A time until the internal state, after transitioning from a first internal state to a second internal state, transitions to the first internal state again is longer than a time interval of updating the state information held by the transition-state acquisition section.
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公开(公告)号：US20230412186A1
公开(公告)日：2023-12-21
申请号：US18461152
申请日：2023-09-05
CPC分类号： H03M1/502 , H03M1/1009 , H03M1/362
摘要： In an example, a system includes an input channel and a voltage to delay converter (V2D) coupled to the input channel. The system also includes a first multiplexer coupled to the V2D and an analog-to-digital converter (ADC) coupled to the first multiplexer. The system includes a second multiplexer coupled to the input channel and an auxiliary ADC coupled to the second multiplexer. The system includes calibration circuitry coupled to an output of the auxiliary ADC, where the calibration circuitry is configured to correct a non-linearity in a signal provided by the input channel. The calibration circuitry is also configured to determine the non-linearity of the signal provided to the ADC relative to the signal provided to the auxiliary ADC.
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46.发明授权公开(公告)号：US11764802B1
公开(公告)日：2023-09-19
申请号：US17704511
申请日：2022-03-25
发明人： Avri Harush
CPC分类号： H03M3/424 , G04F10/005 , H03L7/0991 , H03L7/0995 , H03M1/502 , H03L2207/50
摘要： A digitally-controlled oscillator (DCO) circuit includes a digital-to-analog converter (DAC) to generate a first current based on most significant bits of a multi-bit code received from a time-to-digital converter (TDC) of a digital phase-locked loop (PLL). The DCO circuit further includes a sigma-delta modulator (SDM) to modulate least significant bits of the multi-bit code into a set of digital bits based on a first frequency of a feedback clock of the DPLL. The set of digital bits is to cause the DAC to generate a second current. The DCO circuit further includes a ring oscillator coupled to the DAC, the ring oscillator to generate an alternating-current (AC) output signal having a second frequency corresponding to a combination of the first current and the second current.
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公开(公告)号：US11728822B2
公开(公告)日：2023-08-15
申请号：US17359918
申请日：2021-06-28
发明人： Shahin Mehdizad Taleie , Dongwon Seo , Ashok Swaminathan , Gurkanwal Singh Sahota , Andrew Weil , Haibo Fei
摘要： Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) system. The DAC system generally includes a plurality of current steering cells, each comprising a current source coupled to at least two current steering switches, wherein control inputs of the at least two current steering switches are coupled to an input path of the DAC system. The DAC system may also include a current source toggle circuit configured to selectively disable the current source of at least one of the plurality of current steering cells, and a feedforward path coupled between the input path and at least one control input of the current source toggle circuit.
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公开(公告)号：US10007235B2
公开(公告)日：2018-06-26
申请号：US15711012
申请日：2017-09-21
CPC分类号： G04F10/005 , H03M1/1009 , H03M1/125 , H03M1/502
摘要： A time-to-digital converter (TDC) measures a time interval ΔTTot between a leading signal and a triggering signal. A phase regulator incorporates a looped delay line to create pre-defined sub-intervals TNOR determined by the length of the delay line. The phase regulator has an input receiving the leading signal such that the leading signal loops around the delay line. A counter for counting the number of times m the leading signal loops around the delay line before said triggering signal arrives to obtain a coarse measurement of the time interval defined in terms of the sub-intervals TNOR. A Vernier core for measures a residual time interval TR where TR=ΔTTot−mTNOR to obtain a value for the time interval ΔTTot. The TDC uses simpler encoding logic with reduced power consumption and phase noise performance better than 5 dB.
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公开(公告)号：US10003353B2
公开(公告)日：2018-06-19
申请号：US15652710
申请日：2017-07-18
发明人： Bryan Kris , Jim Bartling , Neil Deutscher
CPC分类号： H03M1/502 , H03K5/14 , H03K5/24 , H03M1/1205
摘要： Embodiments of the present disclosure include voltage comparators. The voltage comparators may include a first input configured to receive a first analog voltage, a second input configured to receive a second analog voltage, a first digital delay line configured to propagate the first analog voltage through a first delay circuit and the second analog voltage through a second circuit, and an output circuit configured to provide a comparator output based upon whether values representing the first analog voltage or the second analog voltage propagated faster through the first digital delay line. The comparator output may be configured to identify whether the first analog voltage or the second analog voltage is greater.
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公开(公告)号：US20170373698A1
公开(公告)日：2017-12-28
申请号：US15685447
申请日：2017-08-24
发明人： Hao YAN , Jiale Huang , Lei Lu
CPC分类号： H03M1/002 , G04F10/005 , H03L7/0814 , H03M1/502
摘要： A time-to-digital converter including N stages of converting circuits, where N≧2, and N is an integer. Each stage of converting circuit includes a first delayer and an arbiter; an output end of the first delayer in each stage of converting circuit outputs a delayed signal of the stage of converting circuit; and the arbiter in each stage of converting circuit receives a sampling clock and the delayed signal of the stage of converting circuit, and compares the sampling clock with the delayed signal to obtain an output signal of the stage of converting circuit. Output signals of the N stages of converting circuits form a non-linear binary number, to indicate a time difference between a clock signal and a reference signal.
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