公开(公告)号：US20100181104A1

公开(公告)日：2010-07-22

申请号：US12666634

申请日：2008-04-22

Applicant: Teruyuki Hotta ,  Shushi Morimoto ,  Takahiro Ishizaki ,  Hisamitsu Yamamoto

Inventor： Teruyuki Hotta ,  Shushi Morimoto ,  Takahiro Ishizaki ,  Hisamitsu Yamamoto

IPC: H05K1/11 ,  H01K3/10

CPC classification number: H05K3/421 ,  H05K3/184 ,  H05K3/422 ,  H05K3/465 ,  H05K3/4661 ,  H05K2203/0733 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: The present invention is directed to a method for manufacturing a printed circuit board in which a plurality of conductive layers forming a wiring pattern are laminated in the state where they are put between insulating layers, and a printed circuit board formed thereby. The printed circuit board manufacturing method for the present invention includes a step of forming a via fill (17) to allow electroless plating liquid to be in contact with the surface of the wiring pattern exposed to a bottom part of a via hole (14) formed at a insulating layer to laminate plating metallic film from the bottom part to a opening part of the via hole (14), to form the via fill (17), and a step of forming a wiring pattern to form electroless plating metallic film (20) serving as the wiring pattern onto a substrate where the via fill (17) is formed.

Abstract translation: 本发明涉及一种制造印刷电路板的方法，其中形成布线图案的多个导电层在它们被放置在绝缘层之间的状态下被层叠，并且由此形成印刷电路板。 本发明的印刷电路板的制造方法包括形成通孔填充物（17）的步骤，以使化学镀液体与暴露于形成的通孔（14）的底部的布线图案的表面相接触 在绝缘层上层叠从底部到通孔（14）的开口部的电镀金属膜，以形成通孔填充物（17），以及形成布线图案以形成化学镀金属膜（20）的步骤 ）作为布线图案，形成在通孔填充物（17）的基板上。

公开(公告)号：US20100032202A1

公开(公告)日：2010-02-11

申请号：US11658877

申请日：2006-07-07

Applicant: Hideki Higashitani

Inventor： Hideki Higashitani

IPC: H05K1/11 ,  H05K3/00

CPC classification number: H05K3/4069 ,  H05K3/0032 ,  H05K3/06 ,  H05K3/384 ,  H05K3/4614 ,  H05K3/465 ,  H05K3/4652 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0373 ,  H05K2201/09827 ,  H05K2203/025 ,  H05K2203/0307 ,  H05K2203/0353 ,  H05K2203/1461 ,  Y10T29/49124

Abstract: A wiring substrate of the invention comprises electrical insulation substrate (1), through-hole (3) formed in the electrical insulation substrate, electrically conductive paste (4) filled inside the through-hole, and wiring traces (11) formed on one or both surfaces of the electrical insulation substrate and electrically connected with the electrically conductive paste, wherein interfaces of the wiring traces in contact with the electrically conductive paste have at least one of an asperate surface and a smooth surface, and a plurality of granular bumps (14) formed further thereon.

Abstract translation: 本发明的布线基板包括电绝缘基板（1），形成在电绝缘基板中的通孔（3），填充在通孔内部的导电浆料（4）和形成在一个或多个 电绝缘基板的两个表面并与导电浆料电连接，其中与导电浆料接触的布线迹线的界面具有平坦表面和光滑表面中的至少一个，以及多个颗粒凸块（14） ）。

公开(公告)号：US20090301997A1

公开(公告)日：2009-12-10

申请号：US12211637

申请日：2008-09-16

Applicant: Yi-Chun Liu

Inventor： Yi-Chun Liu

IPC: H01B13/00

CPC classification number: H05K3/107 ,  H05K3/045 ,  H05K3/184 ,  H05K3/465 ,  H05K3/4661 ,  H05K2201/0236 ,  H05K2203/1173 ,  H05K2203/1338 ,  Y10T29/49155

Abstract: A fabricating process of a structure with an embedded circuit is described as follows. Firstly, a substrate having an upper surface and a lower surface opposite to the upper surface is provided. Afterward, a dielectric layer is formed on the upper surface of the substrate. Next, a plating-resistant layer is formed on the dielectric layer. Then, the plating-resistant layer and the dielectric layer are patterned for forming an recess pattern on the dielectric layer. Subsequently, a conductive base layer is formed in the recess pattern by using a chemical method, and the plating-resistant layer is exposed by the conductive base layer. After that, the plating-resistant layer is removed.

Abstract translation: 具有嵌入电路的结构的制造工艺描述如下。 首先，提供具有与上表面相对的上表面和下表面的基板。 之后，在基板的上表面形成电介质层。 接下来，在电介质层上形成耐电镀层。 然后，对电镀层和电介质层进行图案化以在电介质层上形成凹陷图案。 随后，通过使用化学方法在凹陷图案中形成导电性基底层，并且通过导电性基底层露出耐电镀层。 之后，除去耐电镀层。

公开(公告)号：US20090246462A1

公开(公告)日：2009-10-01

申请号：US12056985

申请日：2008-03-27

Applicant: Houssam Jomaa ,  Amruthavalli P. Alur ,  Dilan Seneviratne

Inventor： Houssam Jomaa ,  Amruthavalli P. Alur ,  Dilan Seneviratne

IPC: B32B3/00 ,  B05D5/12

CPC classification number: H05K3/387 ,  H05K3/0032 ,  H05K3/0055 ,  H05K3/108 ,  H05K3/465 ,  H05K3/4661 ,  H05K2203/066 ,  H05K2203/1152 ,  H05K2203/1383 ,  Y10T428/24355 ,  Y10T428/24612

Abstract: A method of manufacturing a substrate for a microelectronic device comprises providing a dielectric material (120, 220, 920) as a build-up layer of the substrate, applying a primer (140, 240, 940) to a surface (121, 221, 921) of the dielectric material, and forming an electrically conductive layer (150, 250, 950) over the primer. In another embodiment, the method comprises providing the dielectric material, forming the feature extending into the dielectric material, forming the electrically conductive layer over the dielectric material, applying the primer to a surface of the electrically conductive layer and attaching a dielectric layer (960) to the primer.

Abstract translation: 一种制造用于微电子器件的衬底的方法包括提供作为衬底的堆积层的电介质材料（120,220,920），将底漆（140,240,940）施加到表面（121,221， 921），并且在引物上形成导电层（150,250,950）。 在另一个实施方案中，该方法包括提供电介质材料，形成延伸到电介质材料中的特征，在电介质材料上形成导电层，将引物施加到导电层的表面，并附着电介质层（960） 到底漆。

公开(公告)号：US20090071704A1

公开(公告)日：2009-03-19

申请号：US12284324

申请日：2008-09-19

Applicant: Shih-Ping Hsu

Inventor： Shih-Ping Hsu

IPC: H05K1/11 ,  H05K3/10

CPC classification number: H05K3/465 ,  H05K1/09 ,  H05K3/184 ,  H05K3/421 ,  H05K3/422 ,  H05K3/4661 ,  H05K2201/0338 ,  H05K2201/0341 ,  H05K2201/0376 ,  H05K2201/09563 ,  H05K2203/0733 ,  Y10T29/49155

Abstract: A circuit board and a method for fabricating the same are disclosed. The circuit board includes: a carrier board having a circuit layer formed on at least one surface thereof; a first dielectric layer formed on the carrier board and having first openings for exposing a part of the circuit layer; conductive vias formed in the first openings; a second dielectric layer formed on the first dielectric layer and having second and third openings formed therein, wherein the second openings correspond to the first openings for exposing the conductive vias; and a multi-layered metal electroless plating circuit layer formed in the second and third openings for electrically connecting the circuit layer of the carrier board via the conductive vias, thereby allowing the multi-layered metal electroless plating circuit layer to be embedded into the first and second dielectric layers to enhance the bonding strength therebetween and increase the reliability of the circuit board and facilitate formation of fine circuits.

Abstract translation: 公开了一种电路板及其制造方法。 电路板包括：承载板，其具有形成在其至少一个表面上的电路层; 第一电介质层，形成在所述载体板上并具有用于暴露所述电路层的一部分的第一开口; 在第一开口中形成的导电通孔; 第二电介质层，形成在所述第一电介质层上并且具有形成在其中的第二和第三开口，其中所述第二开口对应于用于暴露所述导电通孔的所述第一开口; 以及形成在所述第二和第三开口中的多层金属化学镀电路层，用于经由所述导电通孔电连接所述载体板的电路层，从而允许所述多层金属化学镀电路层嵌入所述第一和第 第二电介质层，以增强它们之间的结合强度，并提高电路板的可靠性并促进精细电路的形成。

公开(公告)号：US20090014411A1

公开(公告)日：2009-01-15

申请号：US12076431

申请日：2008-03-18

Applicant: Ryoichi Watanabe

Inventor： Ryoichi Watanabe

IPC: B05D5/12 ,  H01B13/00

CPC classification number: H05K3/0014 ,  H05K3/045 ,  H05K3/107 ,  H05K3/465 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2203/0156 ,  H05K2203/0264 ,  H05K2203/0537 ,  H05K2203/0769 ,  H05K2203/308

Abstract: A fabrication method for a multilayer printed circuit board includes: forming a first circuit-forming pattern and a first insulation layer, into which the first circuit-forming pattern is inserted, on a first carrier; forming inner circuit patterns and inner insulation layers over the first insulation layer, and forming inner vias connecting the inner circuit patterns positioned on different insulation layers; forming a second circuit-forming pattern on a second carrier and inserting the second circuit-forming pattern into a second insulation layer on an outermost side; removing the first carrier and the second carrier; forming circuit-forming grooves by removing the first circuit-forming pattern and the second circuit-forming pattern, and forming via-forming indentations connected with the circuit-forming grooves; and forming outer circuit patterns and outer vias by filling the circuit-forming grooves and the via-forming indentations with a conductive material. This can provide a thin printed circuit board having high reliability and fine-lined circuits.

Abstract translation: 一种多层印刷电路板的制造方法包括：在第一载体上形成第一电路形成图案和第一电路形成图案插入其中的第一绝缘层; 在所述第一绝缘层上形成内部电路图案和内部绝缘层，以及形成连接位于不同绝缘层上的内部电路图案的内部通孔; 在第二载体上形成第二电路形成图案，并将第二电路形成图案插入最外侧的第二绝缘层; 移除所述第一载体和所述第二载体; 通过去除第一电路形成图案和第二电路形成图案形成电路形成槽，以及形成与电路形成槽连接的通孔形成凹陷; 以及通过用导电材料填充电路形成槽和通孔形成凹陷来形成外部电路图案和外部通孔。 这可以提供具有高可靠性和细线电路的薄印刷电路板。

公开(公告)号：US07438945B2

公开(公告)日：2008-10-21

申请号：US11033340

申请日：2005-01-11

Applicant: Shigetsugu Muramatsu ,  Katsumi Yamazaki

Inventor： Shigetsugu Muramatsu ,  Katsumi Yamazaki

IPC: B05D5/12 ,  B05D3/00

CPC classification number: H05K3/005 ,  H05K3/107 ,  H05K3/4644 ,  H05K3/465 ,  H05K2203/0108 ,  H05K2203/0582 ,  H05K2203/1189 ,  H05K2203/308

Abstract: A method of producing a multilayer interconnection board is disclosed that includes the steps of processing a resin member on an interconnection layer by imprinting press, and removing residue of the resin member at the bottom of a via hole after forming the via hole. In the method of producing a multilayer interconnection board, a thermal setting resin, which has a setting temperature higher than that of the resin member, is applied on a via-connecting portion of the interconnection layer, the resin member is formed on the interconnection layer, an interconnection groove and a via hole are formed by imprinting press on the resin member by using a tool, and an un-cured portion of the high temperature setting resin is dissolved and removed by using a resin solvent. Thereby, residue of the resin member on the thermal setting resin is removed.

Abstract translation: 公开了一种制造多层互连板的方法，其包括通过压印机在互连层上处理树脂部件的步骤，以及在形成通孔之后在通孔的底部除去树脂部件的残留物。 在制造多层互连板的方法中，将具有比树脂构件的设定温度高的设定温度的热定型树脂施加在互连层的过孔连接部分上，树脂构件形成在互连层 通过使用工具通过压印在树脂部件上形成互连槽和通孔，并且通过使用树脂溶剂将高温固化树脂的未固化部分溶解并除去。 由此，除去热固化树脂上的树脂部件的残留物。

公开(公告)号：US20080052904A1

公开(公告)日：2008-03-06

申请号：US11572524

申请日：2005-07-28

Applicant: Reinhard Schneider ,  Hannes Hofmann ,  David Baron

Inventor： Reinhard Schneider ,  Hannes Hofmann ,  David Baron

IPC: H05K3/00

CPC classification number: H01L21/4867 ,  H01L21/486 ,  H01L23/49883 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/3011 ,  H05K1/185 ,  H05K3/107 ,  H05K3/125 ,  H05K3/1258 ,  H05K3/246 ,  H05K3/4069 ,  H05K3/465 ,  H05K3/4664 ,  H05K2201/0329 ,  H05K2201/0347 ,  H05K2201/09036 ,  H05K2203/013 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  H01L2924/00

Abstract: To create very small lines and spaces (≦25 μm, preferably ≧10 μm and being as low as 5 μm) on electronic circuit assemblies with justifiable effort a method is utilized which comprises the following method steps: a) providing a dielectric layer; b) forming a three-dimensional structure in a dielectric layer by laser ablation so as to provide one or more structure elements in the layer selected from the group comprising trenches and component recesses; c) applying a fluid to at least part of surface regions of the dielectric layer exposed in the structure elements, the fluid containing or forming at least one of conductive particles or intrinsic conductive polymer on the surface; and d) metallizing at least part of the surface regions.

Abstract translation: 为了在电子电路组件上以合理的努力创建非常小的线和空间（<=25μm，优选> =10μm并且低至5um），该方法包括以下方法步骤：a）提供介电层 ; b）通过激光烧蚀在电介质层中形成三维结构，以便在选自包括沟槽和部件凹部的组中提供一个或多个结构元件; c）向暴露在结构元件中的电介质层的至少部分表面区域施加流体，所述流体包含或形成表面上的导电颗粒或本征导电聚合物中的至少一种; 和d）金属化至少部分表面区域。

公开(公告)号：US20080023815A1

公开(公告)日：2008-01-31

申请号：US11858942

申请日：2007-09-21

Applicant: Motoo ASAI ,  Kouta Noda ,  Yasushi Inagaki

Inventor： Motoo ASAI ,  Kouta Noda ,  Yasushi Inagaki

IPC: H01L23/24

CPC classification number: H01L23/145 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K3/005 ,  H05K3/045 ,  H05K3/107 ,  H05K3/381 ,  H05K3/4602 ,  H05K3/465 ,  H05K3/4661 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0245 ,  H05K2201/09036 ,  H05K2203/0108 ,  H05K2203/1152 ,  H05K2203/1189 ,  Y10T428/25 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A printed wiring board including a substrate, conductor circuits and interlayer dielectric layers stacked alternately on the substrate, each of the interlayer dielectric layers including a curable resin having flaky particles dispersed therein, and viaholes formed in the interlayer dielectric layers and electrically connecting the conductor circuits at different levels.

Abstract translation: 一种印刷电路板，包括基板，导体电路和层间电介质层，层叠电介质层交替地堆叠在基板上，每个层间介电层包括其中分散有片状颗粒的固化树脂，以及形成在层间电介质层中的通孔，并将导体电路 在不同层次上

公开(公告)号：US20080009100A1

公开(公告)日：2008-01-10

申请号：US11859758

申请日：2007-09-22

Applicant: Peter Davison

Inventor： Peter Davison

IPC: H01L21/44

CPC classification number: H01L21/4867 ,  H05K3/005 ,  H05K3/045 ,  H05K3/107 ,  H05K3/465 ,  H05K2201/09036 ,  H05K2203/0108 ,  H05K2203/0285 ,  H05K2203/1189

Abstract: Embodiments of a method and apparatus for imprinting a trench pattern on a substrate using ultrasonic vibrations. The trench pattern corresponds to a circuit pattern that is to be formed on the substrate, the circuit pattern including a number of conductive traces and other conductive elements. In one embodiment, the substrate includes a base layer and a layer of dielectric material overlying a surface of the base layer, and the circuit pattern is formed in the dielectric layer.

Abstract translation: 用于使用超声波振动将沟槽图案压印在基板上的方法和装置的实施例。 沟槽图案对应于要形成在衬底上的电路图案，该电路图案包括多个导电迹线和其它导电元件。 在一个实施例中，衬底包括基底层和覆盖在基底层的表面上的介电材料层，并且电介质层形成电路图案。