公开(公告)号：US10714344B2

公开(公告)日：2020-07-14

申请号：US16665139

申请日：2019-10-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tien-Shun Chang ,  Chun-Feng Nieh ,  Huicheng Chang

IPC分类号： H01L21/033 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3215 ,  H01L21/266 ,  H01L21/308 ,  H01L21/426

摘要： Embodiments described herein relate generally to methods for forming a mask for patterning a feature in semiconductor processing. In an embodiment, a dielectric layer is formed over a substrate. A mask is formed over the dielectric layer. Forming the mask includes depositing a first layer over the dielectric layer; implanting in a first implant process a dopant species through a patterned material and into the first layer at a first energy; after implanting in the first implant process, implanting in a second implant process the dopant species through the patterned material and into the first layer at a second energy greater than the first energy; and forming mask portions of the mask comprising selectively removing portions of the first layer that are not implanted with the dopant species.

公开(公告)号：US10651030B2

公开(公告)日：2020-05-12

申请号：US16421532

申请日：2019-05-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ming-Chang Wen ,  Chang-Yun Chang ,  Hsien-Chin Lin ,  Hung-Kai Chen

IPC分类号： H01L21/02 ,  H01L21/3215 ,  H01L21/3105 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8258 ,  H01L21/8238 ,  H01L21/762 ,  H01L27/11 ,  H01L27/02

摘要： A semiconductor structure includes a substrate; first and second fins extending from the substrate and oriented lengthwise generally along a first direction; an isolation feature over the substrate and separating bottom portions of the first and the second fins; first and second epitaxial semiconductor features over the first and the second fins, respectively; and a first dielectric feature sandwiched between the first and the second epitaxial semiconductor features. A maximum width of the first dielectric feature is smaller than a width of the isolation feature between the first and the second fins along a second direction perpendicular to the first direction.

公开(公告)号：US20200098534A1

公开(公告)日：2020-03-26

申请号：US16142208

申请日：2018-09-26

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Joshua T. Smith ,  Benjamin Wunsch

IPC分类号： H01J21/10 ,  H01J1/304 ,  H01L29/417 ,  H01L21/3215

摘要： A technique relates to a semiconductor device. An emitter electrode and a collector electrode are formed in a dielectric layer such that a nanogap separates the emitter electrode and the collector electrode, a portion of the emitter electrode including layers. A channel is formed in the dielectric layer so as to traverse the nanogap. A top layer is formed over the channel so as to cover the channel and the nanogap without filling in the channel and the nanogap, thereby forming a vacuum channel transistor structure.

公开(公告)号：US10580487B2

公开(公告)日：2020-03-03

申请号：US16048364

申请日：2018-07-30

申请人： Winbond Electronics Corp.

发明人： Chiang-Hung Chen ,  Yao-Ting Tsai ,  Wen Hung ,  Yu-Kai Liao

IPC分类号： G11C11/56 ,  H01L21/3215 ,  H01L23/532 ,  H01L29/51 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L27/11582 ,  G11C16/04 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/528 ,  H01L21/28 ,  H01L29/423 ,  H01L27/11521 ,  H01L29/66 ,  H01L29/788

摘要： A three dimensional memory includes a substrate, a plurality of source lines, a plurality of isolation structures, a plurality of drain lines, a plurality of bit lines, a plurality of charge storage structures, and a plurality of conductive layers. The source lines are located on the substrate. The isolation structures are respectively located between the source lines, so as to electrically isolate the source lines from each other. The drain lines are located on the source lines. Extending directions of the source lines and the drain lines are different. The bit lines extend from the source lines to the drain lines. The charge storage structures respectively surround the bit lines. The conductive layers respectively cover surfaces of the charge storage structures arranged along each of the source lines.

公开(公告)号：US20200043808A1

公开(公告)日：2020-02-06

申请号：US16051833

申请日：2018-08-01

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Ruqiang BAO ,  Dechao GUO ,  Junli Wang ,  Heng WU

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L21/28 ,  H01L21/3215

摘要： A technique relates to a semiconductor device. An N-type field effect transistor (NFET) and a P-type field effect transistor (PFET) each include an inner work function metal, an outer work function metal, a first nanosheet including an inner channel surface having a first threshold voltage, and a second nanosheet including an outer channel surface having a second threshold voltage. The outer work function metal is modified so as to cause the outer channel surface for the second nanosheet to have the second threshold voltage within a predefined amount of the first threshold voltage for the inner channel surface of the first nanosheet, the predefined amount being within about 20 millivolts (mV).

公开(公告)号：US10522358B2

公开(公告)日：2019-12-31

申请号：US15964253

申请日：2018-04-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun-Chieh Wang ,  Zheng-Yang Pan ,  Shih-Chieh Chang ,  Cheng-Han Lee ,  Huai-Tei Yang ,  Shahaji B. More

IPC分类号： H01L21/28 ,  H01L29/66 ,  H01L27/092 ,  H01L21/3215 ,  H01L29/51 ,  H01L29/78 ,  H01L29/49 ,  H01L21/8238

摘要： A FinFET device and method of forming the same are disclosed. The method includes forming a gate dielectric layer and depositing a metal oxide layer over the gate dielectric layer. The method also includes annealing the gate dielectric layer and the metal oxide layer, causing ions to diffuse from the metal oxide layer to the gate dielectric layer to form a doped gate dielectric layer. The method also includes forming a work function layer over the doped gate dielectric layer, and forming a gate electrode over the work function layer.

公开(公告)号：US20190287802A1

公开(公告)日：2019-09-19

申请号：US15920745

申请日：2018-03-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tien-Shun CHANG ,  Chun-Feng NIEH ,  Huicheng CHANG

IPC分类号： H01L21/033 ,  H01L21/3215 ,  H01L21/311 ,  H01L21/768

摘要： Embodiments described herein relate generally to methods for forming a mask for patterning a feature in semiconductor processing. In an embodiment, a dielectric layer is formed over a substrate. A mask is formed over the dielectric layer. Forming the mask includes depositing a first layer over the dielectric layer; implanting in a first implant process a dopant species through a patterned material and into the first layer at a first energy; after implanting in the first implant process, implanting in a second implant process the dopant species through the patterned material and into the first layer at a second energy greater than the first energy; and forming mask portions of the mask comprising selectively removing portions of the first layer that are not implanted with the dopant species.

公开(公告)号：US20190252488A1

公开(公告)日：2019-08-15

申请号：US16259102

申请日：2019-01-28

申请人： Panasonic Intellectual Property Management Co., Ltd.

发明人： TAKAHIRO KOYANAGI ,  YUUKO TOMEKAWA ,  TAKESHI HARADA ,  YOSHIO KAWASHIMA

IPC分类号： H01L49/02 ,  H01L21/3215 ,  H01L21/285 ,  H01L21/02

CPC分类号： H01L28/40 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02205 ,  H01L21/0228 ,  H01L21/28568 ,  H01L21/3215 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/14609 ,  H01L28/60 ,  H01L28/91

摘要： A capacitor includes a first electrode; a second electrode facing the first electrode; and a dielectric layer which is disposed between the first electrode and the second electrode and which is in contact with the first electrode. The first electrode includes a first portion including an interface between the first electrode and the dielectric layer, the dielectric layer includes a second portion including the interface, and the first portion and the second portion each contain silicon. A concentration distribution of the silicon along a thickness direction of the first portion and the second portion includes a convex portion intersecting the interface.

公开(公告)号：US10361096B2

公开(公告)日：2019-07-23

申请号：US15677091

申请日：2017-08-15

申请人： Infineon Technologies AG

发明人： Mathias Plappert ,  Stefan Krivec ,  Andreas Riegler ,  Karin Schrettlinger

IPC分类号： H01L21/3215 ,  H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L23/29 ,  H01L29/66 ,  H01L29/739 ,  H01L29/40 ,  H01L29/06 ,  H01L29/417 ,  H01L29/74

摘要： In various embodiments, a method is provided. The method includes forming a metallization layer above at least one first region of a substrate. After forming the metallization layer at least one second region of the substrate is free of the metallization layer. The method further includes forming a barrier layer above the at least one first region of the substrate and above the at least one second region of the substrate. The barrier layer in the at least one first region of the substrate directly adjoins the metallization layer. The method further includes removing the barrier layer in the at least one first region of the substrate by drive-in of the barrier layer into the metallization layer.

公开(公告)号：US10304927B2

公开(公告)日：2019-05-28

申请号：US15640966

申请日：2017-07-03

申请人： Intel Corporation

发明人： Glenn A. Glass ,  Anand S. Murthy ,  Tahir Ghani

IPC分类号： H01L21/02 ,  H01L29/06 ,  H01L21/285 ,  H01L29/165 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/167 ,  H01L29/08 ,  H01L29/36 ,  H01L27/092 ,  H01L23/535 ,  H01L29/417 ,  H01L21/3215 ,  H01L21/768 ,  H01L29/778 ,  H01L29/423

摘要： Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.