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    Method and apparatus to speed convergence and control behavior of digital control loop
    42.
    发明授权
    Method and apparatus to speed convergence and control behavior of digital control loop 有权

    公开(公告)号：US11848653B2

    公开(公告)日：2023-12-19

    申请号：US17158974

    申请日：2021-01-26

    申请人： MACOM Technology Solutions Holdings, Inc.

    发明人： Vasilis Papanikolaou ,  George L. Barrier, IV

    IPC分类号： H03G3/30 ,  H03G3/00 ,  H03K21/40 ,  H03G3/20

    CPC分类号： H03G3/001 ,  H03G3/20 ,  H03K21/40

    摘要： A system to control convergence of a loop to a reference value. A device, under control of the control loop, generates an output signal. A comparator compares the output signal to a reference value. Responsive to the output signal being less than the reference value, outputting an up signal and, responsive to the output signal being greater than the reference value, outputting a down signal. A counter is configured to maintain a counter value which is incremented in response to an up signal and decremented in response to a down signal. The counter outputs a gain control value. An up/down signal tracker is configured to track a pattern of up signals and down signals and compare the tracked pattern to one or more predetermined patterns such that, responsive to the up signals and down signals matching one of the one or more predetermined patterns, the counter size is decreased.

    PLAY MUTE CIRCUIT AND METHOD
    45.
    发明公开
    PLAY MUTE CIRCUIT AND METHOD 审中-公开

    公开(公告)号：US20230378923A1

    公开(公告)日：2023-11-23

    申请号：US17747845

    申请日：2022-05-18

    申请人： STMicroelectronics S.r.l. ,  STMicroelectronics (Shenzhen) R&D Co. Ltd.

    发明人： Jian Wen ,  Davide Luigi Brambilla ,  Qiyu Liu ,  Mei Yang ,  Shuming Tong ,  Francesco Stilgenbauer

    IPC分类号： H03G3/30 ,  H03G3/34 ,  H03K4/06

    CPC分类号： H03G3/3026 ,  H03G3/348 ,  H03G3/3036 ,  H03K4/06

    摘要： In an embodiment, an amplifier circuit includes a second stage that includes a first switch circuit including first and second terminals, a plurality of resistive elements coupled between the first and second terminals of the first switch circuit, and a plurality of switches configured to control an equivalent resistance between the first and second terminals of the first switch circuit. During play mode, the second stage has a gain between the input of the second stage and the output of the second stage of a first value. During a transition from mute mode to play mode, the amplifier circuit is configured to progressively increase the gain of the second stage from a second value to the first value. During a transition from play mode to mute mode, the amplifier circuit is configured to progressively decrease the gain of the second stage from the first value to the second value.

    RADIO FREQUENCY LOW NOISE AMPLIFIERS
    46.
    发明公开
    RADIO FREQUENCY LOW NOISE AMPLIFIERS 审中-公开

    公开(公告)号：US20230370029A1

    公开(公告)日：2023-11-16

    申请号：US18359718

    申请日：2023-07-26

    申请人： Huawei Technologies Co., Ltd.

    发明人： William Roeckner ,  Terrie McCain ,  Matthew Miller

    IPC分类号： H03F3/24 ,  H03F1/56 ,  H03G3/30

    CPC分类号： H03F3/245 ,  H03F1/56 ,  H03G3/3036 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2200/255 ,  H03G2201/103 ,  H03G2201/307

    摘要： Methods, systems, and apparatus, including computer programs encoded on computer storage media, for a programmable input impedance circuit for a radio frequency (RF) low noise amplifier (LNA) including a high impedance mode circuit and a low impedance mode circuit. The high impedance mode circuit includes an inductor-degenerated transconductor transistor, an inductor selectively coupled between a source of the inductor-degenerated transconductor transistor and a ground, and a capacitor coupled between a gate of the inductor-degenerated transconductor transistor and the source of the inductor-degenerated transconductor transistor. The low impedance mode circuit includes a shunt resistor selectively coupled between an RF input source and an alternating current (AC) ground.

    Circuitry for and Methods of Gain Control
    47.
    发明公开
    Circuitry for and Methods of Gain Control 审中-公开

    公开(公告)号：US20230353111A1

    公开(公告)日：2023-11-02

    申请号：US17982864

    申请日：2022-11-08

    申请人： Cirrus Logic International Semiconductor Ltd.

    发明人： Andrew J. HOWLETT ,  Michael CHANDLER-PAGE ,  David P. SINGLETON ,  Erich P. ZWYSSIG

    IPC分类号： H03G3/30 ,  H03F3/04

    CPC分类号： H03G3/30 ,  H03F3/04 ,  H03G2201/103

    摘要： An integrated circuit (IC), comprising: a first input pin for receiving a first input signal; a first converter configured to convert the first input signal to a first output signal; a first gain stage configured to apply a first gain to the first output signal; gain update circuitry configured to: output a first external gain control signal to a first output pin of the IC; and subsequently output a first internal gain control signal to the first gain stage to update the first gain of the first gain stage, wherein output of the first internal gain control signal is delayed relative to output of the first external gain control signal by a first predetermined delay, the first predetermined delay to compensate for signal chain delay between the first input pin and the first gain stage.