公开(公告)号：US12096613B2

公开(公告)日：2024-09-17

申请号：US17510046

申请日：2021-10-25

Applicant: Micron Technology, Inc.

Inventor： Naokazu Murata

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/315 ,  H10B12/50

Abstract: Apparatuses and methods for controlling hydrogen diffusion to a substrate in manufacturing memory devices are described. An example apparatus includes: a substrate; an active region in the substrate; at least one first conductive material above the active region; a hydrogen source layer on the at least one first conductive material, the hydrogen source layer including hydrogen atoms and/or molecules and the hydrogen source layer configured to release the hydrogen atoms and/or molecules; a hydrogen diffusion barrier layer on the conductive layer; and at least one second conductive material above the hydrogen diffusion barrier layer, the at least one second conductive material coupled to the at least one first conductive material. The at least one first conductive material has hydrogen diffusion properties. The hydrogen diffusion barrier layer has hydrogen barrier properties.

公开(公告)号：US12094549B2

公开(公告)日：2024-09-17

申请号：US17889578

申请日：2022-08-17

Applicant: Micron Technology, Inc.

Inventor： Jun Xu ,  Kitae Park

IPC: G11C29/12 ,  G11C16/10 ,  G11C16/14 ,  G11C16/34

CPC classification number: G11C29/12 ,  G11C16/10 ,  G11C16/14 ,  G11C16/3445 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: A system includes a memory device including a memory array and control logic, operatively coupled with the memory array, to perform operations including causing an erase operation to be performed. The erase operation includes sub-operations. The operations further include causing defect detection to be performed during at least one sub-operation of the sub-operations. The defect detection is performed using at least one defect detection method with respect to at least one failure point.

公开(公告)号：US12094531B2

公开(公告)日：2024-09-17

申请号：US17146314

申请日：2021-01-11

Applicant: Micron Technology, Inc.

Inventor： Aliasger Tayeb Zaidy ,  Patrick Alan Estep ,  David Andrew Roberts

IPC: G06F3/06 ,  G06F12/0862 ,  G06F12/0897 ,  G06N3/063 ,  G06N3/08 ,  G11C11/54

CPC classification number: G11C11/54 ,  G06F12/0862 ,  G06F12/0897 ,  G06N3/063 ,  G06N3/08

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, the accelerator can have processing units to perform at least matrix computations of an artificial neural network via execution of instructions. The processing units have a local memory store operands of the instructions. The accelerator can access a random access memory via a system buffer, or without going through the system buffer. A fetch instruction can request an item, available at a memory address in the random access memory, to be loaded into the local memory at a local address. The fetch instruction can include a hint for the caching of the item in the system buffer. During execution of the instruction, the hint can be used to determine whether to load the item through the system buffer or to bypass the system buffer in loading the item.

公开(公告)号：US12094512B2

公开(公告)日：2024-09-17

申请号：US17896345

申请日：2022-08-26

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Andrea Locatelli

IPC: G11C11/22

CPC classification number: G11C11/2295 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2293 ,  G11C11/2297

Abstract: Systems and methods described herein may enable a memory system to selectively provide a signal boost to a memory cell in response to a change in operating condition, like a change in temperature. The systems and methods may include determining to generate a signal boost for a first duration of time and in response to determining to generate the signal boost, generating the signal boost causing an increase in voltage applied to a signal line coupled to a memory cell. The systems and methods may further include, after the first duration of time, ceasing generation of the signal boost.

公开(公告)号：US12093566B2

公开(公告)日：2024-09-17

申请号：US17684129

申请日：2022-03-01

Applicant: Micron Technology, Inc.

Inventor： Nicola Del Gatto ,  Emanuele Confalonieri ,  Paolo Amato ,  Patrick Estep ,  Stephen S. Pawlowski

IPC: G06F3/06 ,  G06F12/0864

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0622 ,  G06F3/0656 ,  G06F3/0689 ,  G06F12/0864

Abstract: A memory controller can include a front end portion configured to interface with a host, a central controller portion configured to manage data, a back end portion configured to interface with memory devices. The memory controller can include interface management circuitry coupled to a cache and a memory device. The memory controller can receive, by the interface management controller, a first signal indicative of data associated with a memory access request from a host. The memory controller can transmit a second signal indicative of the data to cache the data in a first location in the cache. The memory controller can transmit a third signal indicative of the data to cache the data in a second location in the cache.

公开(公告)号：US20240305507A1

公开(公告)日：2024-09-12

申请号：US18584986

申请日：2024-02-22

Applicant: Micron Technology, Inc.

Inventor： Chulkyu Lee ,  Timothy M. Hollis

IPC: H04L25/03 ,  G06F13/16

CPC classification number: H04L25/03267 ,  G06F13/1668 ,  H04L25/03057

Abstract: Methods, apparatuses, and systems related to an apparatus for managing on-die inter-symbol interference (ISI) are described. The apparatus may include (1) a single communication path with a set of drivers and (2) an on-die ISI prevention circuit coupled to the communication path in parallel. The single communication path may be used to propagate a slower speed signal and a higher speed signal. The on-die ISI prevention circuit may be configured to adjust the propagated signal for one of the speeds to reduce the ISI in the communicated signal.

公开(公告)号：US20240305449A1

公开(公告)日：2024-09-12

申请号：US18665153

申请日：2024-05-15

Applicant: Micron Technology, Inc.

Inventor： Olivier Duval

IPC: H04L9/08 ,  G06F11/32 ,  G06Q50/10 ,  H04L9/32 ,  H04L67/306 ,  H04L67/51

CPC classification number: H04L9/0825 ,  G06F11/323 ,  G06Q50/10 ,  H04L9/0866 ,  H04L9/3247 ,  H04L67/306 ,  H04L67/51

Abstract: Various examples are directed to a system for configuring a host device. The host device may comprise a memory system and may be programmed to receive subscriber software for interfacing the host device to a subscription service. The host device may also be programmed to receive from a first assembler secure appliance, first trace data based at least in part on the subscriber software and generate trace-derived data using the first trace data and the memory system identification key. The host device may also be programmed to send a subscription request to a subscription server associated with the subscription service. The subscription request may comprise the trace-derived data. The host device may also be programmed to receive, from the subscription server, subscription data for accessing the subscription service.

公开(公告)号：US20240304371A1

公开(公告)日：2024-09-12

申请号：US18431817

申请日：2024-02-02

Applicant: Micron Technology, Inc.

Inventor： Dustin L. Holloway ,  Jonathan S. Parry

IPC: H01F27/28 ,  H01F27/02 ,  H01F27/26 ,  H01F41/04 ,  H01L25/16

CPC classification number: H01F27/2804 ,  H01F27/022 ,  H01F27/266 ,  H01F27/2823 ,  H01F41/041 ,  H01L25/16 ,  H01F2027/2814

Abstract: A semiconductor assembly is provided. The assembly includes a substrate and an inductor. The inductor includes a magnetic core with a first row of first bond pads on a first side and a second row of second bonds pads on a second side, the second side being opposite to the first side. The inductor further includes a plurality of wire bonds, each wire bond connecting a topside of one of the first bond pads to a topside of one of the second bond pads by running over the magnetic core, and a plurality of electrical traces connecting an underside of one of the first bond pads to an underside of one of the second bond pads by running under the magnetic core and through the substrate.

公开(公告)号：US20240304253A1

公开(公告)日：2024-09-12

申请号：US18423174

申请日：2024-01-25

Applicant: Micron Technology, Inc.

Inventor： Hernan Castro

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C16/102 ,  G11C16/0433 ,  G11C16/26

Abstract: Systems, methods, and apparatus related to memory devices that perform multiplication using sets of memory cells. In one approach, memory cells in the sets are programmed so that each set stores a signed weight. Voltage drivers apply voltages to the memory cells in each set. The voltages correspond to signed inputs to multiply by the signed weights in the sets. One or more common lines (e.g., bitlines) are coupled to each set for summing output currents from the sets. A digitizer provides a signed result based on summing the output currents from the sets.

公开(公告)号：US20240304233A1

公开(公告)日：2024-09-12

申请号：US18667802

申请日：2024-05-17

Applicant: Micron Technology, Inc.

Inventor： Jin Seung Son ,  Mingdong Cui

IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/4096

CPC classification number: G11C11/4087 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/4096

Abstract: The disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the array and comprising a first and second n-type transistor having a first and second gate, respectively, and pre-decoder circuity to provide a bias condition for the first and second gate to provide a selection signal to one of the cells. The bias condition comprises a positive voltage for the first gate and a negative voltage for the second gate for a positive memory cell configuration, and zero volts for the first gate and the negative voltage for the second gate for a negative memory cell configuration. The pre-decoder circuitry comprises first pre-decoder circuitry to provide the positive voltage for the first gate and the zero volts for the second gate and second pre-decoder circuitry to provide the negative voltage for the second gate.