公开(公告)号：US10366757B2

公开(公告)日：2019-07-30

申请号：US16126316

申请日：2018-09-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien Delalleau

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/14 ,  H01L29/423 ,  G11C16/12 ,  G11C16/26 ,  H01L27/11521 ,  H01L27/11556 ,  G11C16/10

Abstract: A non-volatile memory cell includes a selection transistor having an insulated selection gate embedded in a semiconducting substrate region. A semiconducting source region contacts a lower part of the insulated selection gate. A state transistor includes a floating gate having an insulated part embedded in the substrate region above an upper part of the insulated selection gate, a semiconducting drain region, and a control gate insulated from the floating gate and located partially above the floating gate. The source region, the drain region, the substrate region, and the control gate are individually polarizable.

公开(公告)号：US10354063B2

公开(公告)日：2019-07-16

申请号：US15442303

申请日：2017-02-24

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Ibrahima Diop ,  Pierre-Yvan Liardet ,  Yanis Linge

IPC: G06F21/52 ,  G06F7/523 ,  G06F7/72

Abstract: A method of protecting a modular calculation on a first number and a second number, executed by an electronic circuit, including the steps of: combining the second number with a third number to obtain a fourth number; executing the modular calculation on the first and fourth numbers, the result being contained in a first register or memory location; initializing a second register or memory location to the value of the first register or to one; and successively, for each bit at state 1 of the third number: if the corresponding bit of the fourth number is at state 1, multiplying the content of the second register or memory location by the inverse of the first number and placing the result in the first register or memory location, if the corresponding bit of the fourth number is at state 0, multiplying the content of the second register or memory location by the first number and placing the result in the first register or memory location.

公开(公告)号：US20190214434A1

公开(公告)日：2019-07-11

申请号：US16357152

申请日：2019-03-18

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe BOIVIN ,  Simon JEANNOT

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2436 ,  G11C13/0004 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1666

Abstract: The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.

公开(公告)号：US20190214341A1

公开(公告)日：2019-07-11

申请号：US16242529

申请日：2019-01-08

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak MARZAKI ,  Arnaud REGNIER ,  Stephan NIEL

IPC: H01L23/522 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L23/5223 ,  H01L21/0214 ,  H01L21/76224 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0805 ,  H01L29/66181 ,  H01L29/945

Abstract: A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.

公开(公告)号：US10345142B2

公开(公告)日：2019-07-09

申请号：US15444529

申请日：2017-02-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Clement Champeix

IPC: G01J1/42 ,  G01J1/44 ,  G06F21/87 ,  H01L23/00 ,  H01L31/112

Abstract: A laser detection device can be used to protect an integrated circuit. The device includes a detection cell having a buried channel of a first conductivity type extending in a substrate of the integrated circuit. The substrate is of a second conductivity type. The detection cell also has a first electrical connection coupling a first point in the buried channel to a supply voltage rail, and a second electrical connection coupled to a second point in the buried channel. A detection circuit is coupled to the second point in the buried channel via the second electrical connection and adapted to detect a fall in the voltage at the second point.

公开(公告)号：US10317846B2

公开(公告)日：2019-06-11

申请号：US15868484

申请日：2018-01-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara

IPC: G11C16/04 ,  H01L27/115 ,  G04F10/10 ,  G11C16/28 ,  G11C16/34 ,  G11C27/00 ,  H01L21/28 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66 ,  H01L29/788 ,  H01L29/51

Abstract: An EEPROM memory cell includes a dual-gate MOS transistor in which the two gates are separated by an insulation layer. The insulation layer includes a first portion and a second portion having lower insulation properties than the first one. The second portion is located at least partially above a channel region of the transistor.

公开(公告)号：US20190165105A1

公开(公告)日：2019-05-30

申请号：US16241762

申请日：2019-01-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Guilhem BOUTON ,  Pascal FORNARA ,  Christian RIVERO

IPC: H01L29/10 ,  H01L27/112 ,  H01L29/78 ,  H01L21/763 ,  H01L21/762 ,  H01L29/06

Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.

公开(公告)号：US10304524B2

公开(公告)日：2019-05-28

申请号：US15630614

申请日：2017-06-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: H01L29/788 ,  G11C11/41 ,  G11C11/412 ,  G11C14/00 ,  G11C16/04 ,  H01L27/11 ,  H01L23/522 ,  H01L29/08 ,  H01L29/423 ,  H01L29/51

Abstract: A semiconductor structure includes first and second source/drain region disposed in a semiconductor body and spaced from each other by a channel region. A gate electrode overlies the channel region and a capacitor electrode is disposed between the gate electrode and the channel region. A first gate dielectric is disposed between the gate electrode and the capacitor electrode and a second gate dielectric disposed between the capacitor electrode and the channel region. A first electrically conductive contact region is in electrical contact with the gate electrode and a second electrically conductive contact region in electrical contact with the capacitor electrode. The first and second contact regions are electrically isolated from one another.

公开(公告)号：US10303234B2

公开(公告)日：2019-05-28

申请号：US15883216

申请日：2018-01-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Bruno Gailhard

IPC: G06F1/28 ,  H02H3/24 ,  H03K5/08 ,  G01R19/165 ,  H02H1/06 ,  H02H3/05 ,  H02H3/247 ,  H02M1/00

Abstract: An integrated processing unit is supplied by a power supply voltage present at the terminals of a capacitor configured to supply a maximum permissible voltage drop. A periodic pulse signal is generated having a period that is less than or equal to a current period determined from the maximum permissible voltage drop and a current consumption of the processing unit. The power supply voltage is compared with a threshold voltage at the pulse rate of the periodic pulse signal. A control signal generated from that comparison is delivered to the processing unit and has a first value when the power supply voltage is greater than or equal to the threshold voltage and a second value when the power supply voltage is less than the threshold voltage.

公开(公告)号：US10298109B2

公开(公告)日：2019-05-21

申请号：US15949690

申请日：2018-04-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Jean-Francois Link ,  Vincent Onde

IPC: H02M1/08 ,  H03K4/08 ,  H03K3/017 ,  H03K7/08 ,  H02M1/00

Abstract: A control signal is applied to a pulse generating circuit configured to generate pulses that are modulated in width. A circuit provides for slope-compensation of the control signal. The circuit includes a digital-to-analog converter that generates a decreasing sawtooth signal. A triggering circuit operates to trigger steps of the sawtooth signal and resetting the sawtooth signal. The sawtooth signal is reset at a cadence of a frequency of the pulses that are modulated in width.