公开(公告)号：US11187613B2

公开(公告)日：2021-11-30

申请号：US16863303

申请日：2020-04-30

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Philippe Grosse ,  Patrick Le Maitre ,  Jean-Francois Carpentier

IPC: G01M11/02 ,  G02B6/28 ,  G02B6/34 ,  G02B6/12 ,  G02B6/00 ,  G01M11/00 ,  G01R31/265 ,  G01R31/27 ,  G01R31/28 ,  G01R31/303 ,  G01R31/311 ,  G01R31/317 ,  G01R35/00

Abstract: An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.

公开(公告)号：US11152259B2

公开(公告)日：2021-10-19

申请号：US16881689

申请日：2020-05-22

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Magali Gregoire

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: An interconnection element of an interconnection structure of an integrated circuit is manufactures by a method where a cavity is etched in an insulating layer. A silicon nitride layer is then deposited on walls and a bottom of the cavity. The nitrogen atom concentration in the silicon nitride layer increasing as a distance from an exposed surface of the silicon nitride layer increases. A copper layer is deposited on the silicon nitride layer. The cavity is further filled with copper. A heating process is performed after the deposition of the copper layer, to convert the copper layer and the silicon nitride layer to form a copper silicide layer which has a nitrogen atom concentration gradient corresponding to the gradient of the silicon nitride layer.

公开(公告)号：US11145779B2

公开(公告)日：2021-10-12

申请号：US16294645

申请日：2019-03-06

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Charles Baudot ,  Sebastien Cremer ,  Nathalie Vulliet ,  Denis Pellissier-Tanon

IPC: H01L27/092 ,  H01L29/16 ,  H01L29/04 ,  H01L29/20 ,  H01L31/109 ,  H01L31/18 ,  H01L31/0232 ,  H01L31/028 ,  H01L31/105

Abstract: A photodiode includes an active area formed by intrinsic germanium. The active area is located within a cavity formed in a silicon layer. The cavity is defined by opposed side walls which are angled relative to a direction perpendicular to a bottom surface of the silicon layer. The angled side walls support epitaxial growth of the intrinsic germanium with minimal lattice defects.

公开(公告)号：US11131782B2

公开(公告)日：2021-09-28

申请号：US16677005

申请日：2019-11-07

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Gilles Gasiot ,  Fady Abouzeid

IPC: G01T1/24 ,  H01L27/07 ,  H01L31/103

Abstract: A diode and a transistor are connected in parallel. The transistor is located on a first doped region forming a PN junction of the diode with a second doped region located under the first region. The circuit functions as an ionizing radiation detection cell by generating a current through the PN junction which changes by a voltage generated across the transistor. This change in voltage is compared to a threshold to detect the ionizing radiation.

公开(公告)号：US20210288102A1

公开(公告)日：2021-09-16

申请号：US17327364

申请日：2021-05-21

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Frederic LALANNE ,  Laurent GAY ,  Pascal FONTENEAU ,  Yann HENRION ,  Francois GUYADER

IPC: H01L27/146

Abstract: Image sensors and methods of manufacturing image sensors are provided herein. In an embodiment, a method of manufacturing an image sensor includes forming a structure having a front side and a back side. The structure includes a semiconductor layer extending between the front side and the back side of the structure, and a capacitive insulation wall extending through the semiconductor layer between the front side and the back side of the structure. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductive or semiconductor material. The method further includes selectively etching, from the back side of the structure, portions of the semiconductor layer and the region of conductive or semiconductor material, while retaining adjacent portions of the first and second insulating walls.

公开(公告)号：US11089252B2

公开(公告)日：2021-08-10

申请号：US16254821

申请日：2019-01-23

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Frederic Lalanne ,  Pierre Malinge

IPC: H04N5/3745 ,  H04N5/353 ,  H04N5/378

Abstract: A pixel includes a photosensitive circuit, a sense node, a first transistor and a first capacitor. A first electrode of the first capacitor is connected to a control terminal of the first transistor. A second electrode of the first capacitor is to a node of application of a first control signal.

公开(公告)号：US11081488B2

公开(公告)日：2021-08-03

申请号：US17026874

申请日：2020-09-21

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak Marzaki ,  Arnaud Regnier ,  Stephan Niel ,  Quentin Hubert ,  Thomas Cabout

IPC: H01L27/108 ,  H01L29/66 ,  H01L29/94 ,  H01L49/02

Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.

公开(公告)号：US11038017B2

公开(公告)日：2021-06-15

申请号：US16279361

申请日：2019-02-19

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Alexis Gauthier ,  Julien Borrel

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/167 ,  H01L29/66 ,  H01L29/737 ,  H01L29/732 ,  H01L21/265

Abstract: A bipolar junction transistor includes an extrinsic collector region buried in a semiconductor substrate under an intrinsic collector region. Carbon-containing passivating regions are provided to delimit the intrinsic collector region. An insulating layer on the intrinsic collector region includes an opening within which an extrinsic base region is provided. A semiconductor layer overlies the insulating layer, is in contact with the extrinsic base region, and includes an opening with insulated sidewalls. The collector region of the transistor is provided between the insulated sidewalls.

公开(公告)号：US11018096B2

公开(公告)日：2021-05-25

申请号：US16210149

申请日：2018-12-05

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Eric Sabouret ,  Krysten Rochereau ,  Olivier Hinsinger ,  Flore Persin-Crelerot

IPC: H01L21/66 ,  H01L23/00 ,  H05K3/34 ,  H01L23/498

Abstract: An integrated circuit includes a solder pad which includes, in a superposition of metallization levels, an underlying structure formed by a network of first regular metal tracks that are arranged for reinforcing the mechanical strength of the underlying structure and electrically connecting between an upper metallization level and a lower metallization level of the underlying structure. The underlying structure further includes a detection electrical path formed by second metal tracks passing between the first metal tracks in the metallization levels, the detection electrical path having an input terminal and an output terminal. Electrical sensing of the detection electrical path is made to supply a measurement which is indicative of the presence of cracks in the underlying structure.

公开(公告)号：US10998236B2

公开(公告)日：2021-05-04

申请号：US16582576

申请日：2019-09-25

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Loic Gaben

IPC: H01L21/8234 ,  H01L21/02 ,  H01L23/52 ,  H01L27/088 ,  H01L21/48 ,  H01L29/06 ,  H01L29/66 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/786 ,  H01L27/092 ,  H01L29/775 ,  B82Y40/00 ,  H01L21/311

Abstract: A strip made of a semiconductor material is formed over a substrate. Longitudinal portions of the strip having a same length are covered with sacrificial gates made of an insulating material and spaced apart from each other. Non-covered portions of the strip are doped to form source/drain regions. An insulating layer followed by a layer of a temporary material is then deposited. Certain ones of the sacrificial gates are left in place. Certain other ones of the sacrificial gates are replaced by a metal gate structure. The temporary material is then replaced with a conductive material to form contacts to the source/drain regions.