公开(公告)号：US09054907B2

公开(公告)日：2015-06-09

申请号：US14148470

申请日：2014-01-06

Applicant: Rambus Inc.

Inventor： Aliazam Abbasfar

IPC: H04L25/03 ,  H04L25/497 ,  H03K5/135

CPC classification number: H04L25/03019 ,  H03K5/135 ,  H03K5/15 ,  H04L25/03878 ,  H04L25/03885 ,  H04L25/497

Abstract: A multi-phase partial response equalizer circuit includes sampler circuits that sample an input signal to generate sampled signals in response to sampling clock signals having different phases. A first multiplexer circuit selects one of the sampled signals as a first sampled bit to represent the input signal. A first storage circuit coupled to an output of the first multiplexer circuit stores the first sampled bit in response to a first clock signal. A second multiplexer circuit selects one of the sampled signals as a second sampled bit to represent the input signal based on the first sampled bit. A second storage circuit stores a sampled bit selected from the sampled signals in response to a second clock signal. A time period between the second storage circuit storing a sampled bit and the first storage circuit storing the first sampled bit is substantially greater than a unit interval in the input signal.

Abstract translation: 多相部分响应均衡器电路包括采样器电路，其对输入信号进行采样以响应具有不同相位的采样时钟信号产生采样信号。 第一多路复用器电路选择一个采样信号作为第一采样位以表示输入信号。 耦合到第一多路复用器电路的输出的第一存储电路响应于第一时钟信号而存储第一采样位。 第二多路复用器电路根据第一采样位选择一个采样信号作为第二采样位来表示输入信号。 第二存储电路响应于第二时钟信号存储从采样信号中选择的采样位。 存储采样位的第二存储电路与存储第一采样位的第一存储电路之间的时间段基本上大于输入信号中的单位间隔。

公开(公告)号：US09047942B2

公开(公告)日：2015-06-02

申请号：US14458212

申请日：2014-08-12

Applicant: Rambus Inc.

Inventor： Scott C. Best

IPC: G11C7/00 ,  G11C14/00 ,  G06F12/06 ,  G06F13/16 ,  G06F12/02

CPC classification number: G11C14/0018 ,  G06F12/0246 ,  G06F12/0638 ,  G06F13/1694

Abstract: Non-transitory computer-readable media having information embodied therein that includes a description of an integrated circuit device. The information includes descriptions of a volatile storage die having a first addressable range of storage cells and a non-volatile storage die. The description of the non-volatile storage die having a second addressable range of storage cells that defines an overlapping region with the first addressable range of storage cells. The information also includes a description of an interface circuit coupled to the volatile and non-volatile storage die to selectively transfer data stored in the overlapping region of storage cells between the die.

Abstract translation: 具有体现在其中的信息的非瞬时计算机可读介质包括集成电路设备的描述。 该信息包括具有第一可寻址范围的存储单元和非易失性存储管芯的易失性存储管芯的描述。 具有第二可寻址范围的存储单元的非易失性存储管芯的描述，其定义与存储单元的第一可寻址范围重叠的区域。 该信息还包括耦合到易失性和非易失性存储管芯的接口电路的描述，以选择性地传输存储在管芯之间的存储单元的重叠区域中的数据。

公开(公告)号：US20150145581A1

公开(公告)日：2015-05-28

申请号：US14539564

申请日：2014-11-12

Applicant: Rambus Inc.

Inventor： Robert E. Palmer ,  Michael D. Bucher ,  Andrew M. Fuller

IPC: H03K5/13 ,  H03K5/135

CPC classification number: H03K5/131 ,  H03K5/135 ,  H03K2005/00058

Abstract: A controllable delay element includes a delay element to provide a variable delay from an input signal to an output signal. The variable delay can be controlled by a digital delay input. The delay element has a delay range that is controlled in response to a delay range input. The delay range of the delay element can be calibrated to a desired range of delays in response to a relative delay between a first timing reference and a second timing reference. A common timing reference is applied to a plurality of receivers and a strobe receiver. The delay through the strobe receiver is adjusted to measure the delay mismatches between the plurality of receivers. The mismatches are used to select a value for the delay through the strobe receiver.

Abstract translation: 可控延迟元件包括延迟元件以提供从输入信号到输出信号的可变延迟。 可变延迟可以通过数字延迟输入来控制。 延迟元件具有响应于延迟范围输入而被控制的延迟范围。 可以响应于第一定时参考和第二定时参考之间的相对延迟，将延迟元件的延迟范围校准到期望的延迟范围。 公共定时参考应用于多个接收机和选通接收机。 通过选通接收机的延迟被调整以测量多个接收机之间的延迟不匹配。 不匹配用于通过选通接收器选择延迟的值。

公开(公告)号：US09043633B2

公开(公告)日：2015-05-26

申请号：US14546687

申请日：2014-11-18

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton ,  Andrew M. Fuller

IPC: G06F1/04 ,  G06F1/08 ,  G06F1/12 ,  G11C7/04 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G06F13/16 ,  G06F1/32 ,  G06F9/38

CPC classification number: G06F1/3237 ,  G06F1/12 ,  G06F1/3225 ,  G06F1/324 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/0629 ,  G06F3/0673 ,  G06F9/3836 ,  G06F12/0857 ,  G06F13/1689 ,  G06F13/36 ,  G06F2201/88 ,  G11C7/04 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/2254 ,  Y02D10/14

Abstract: An integrated-circuit memory controller outputs to a memory device a first signal in a first state to enable operation of synchronous data transmission and reception circuits within the memory device. A transaction queue within the memory controller stores memory read and write requests that, to be serviced, require operation of the synchronous data transmission and reception circuits, respectively, within the memory device. Power control circuitry within the memory controller determines that the transaction queue has reached a predetermined state and, in response, outputs the first signal to the memory device in a second state to disable operation of the synchronous data transmission and reception circuits within the memory device.

Abstract translation: 集成电路存储器控制器向存储器件输出处于第一状态的第一信号，以使存储器件内的同步数据发送和接收电路能够操作。 存储器控制器内的事务队列存储要被服务的存储器读和写请求，分别要求存储器件内的同步数据发送和接收电路的操作。 存储器控制器内的电源控制电路确定事务队列已经达到预定状态，并且作为响应，在第二状态下将第一信号输出到存储器件，以禁止存储器件内的同步数据发送和接收电路的操作。

公开(公告)号：US09037949B1

公开(公告)日：2015-05-19

申请号：US13846200

申请日：2013-03-18

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Suresh N. Rajan ,  Ian P. Shaeffer ,  Frederick A. Ware ,  Wayne F. Ellis

IPC: G11C29/00 ,  G06F11/10

CPC classification number: G06F11/1076 ,  G06F11/1048 ,  G06F11/108 ,  G11C11/40 ,  G11C29/24 ,  G11C29/42 ,  G11C29/44 ,  G11C29/50016

Abstract: A dynamic random access memory (DRAM) array is configured for selective repair and error correction of a subset of the array. Error-correcting code (ECC) is provided to a selected subset of the array to protect a row or partial row of memory cells where one or more weak memory cells are detected. By adding a sense amplifier stripe to the edge of the memory array, the adjacent edge segment of the array is employed to store ECC information associated with the protected subsets of the array. Bit replacement is also applied to defective memory cells. By implementing ECC selectively rather than to the entire array, integrity of the memory array is maintained at minimal cost to the array in terms of area and energy consumption.

Abstract translation: 动态随机存取存储器（DRAM）阵列被配置用于阵列的子集的选择性修复和纠错。 将纠错码（ECC）提供给阵列的选定子集，以保护检测到一个或多个弱存储器单元的行或部分行的存储单元。 通过向存储器阵列的边缘添加感测放大器条纹，阵列的相邻边缘段用于存储与阵列的受保护子集相关联的ECC信息。 位更换也适用于有缺陷的存储单元。 通过有选择地执行ECC而不是整个阵列，在面积和能量消耗方面，以阵列的最低成本保持存储器阵列的完整性。

公开(公告)号：US09009400B2

公开(公告)日：2015-04-14

申请号：US14023970

申请日：2013-09-11

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Amir Amirkhany ,  Suresh Rajan ,  Mohammad Hekmat ,  Dinesh Patil

IPC: G06F13/00 ,  G11C7/10 ,  G11C8/18 ,  G11C11/419 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/02

CPC classification number: G06F13/1673 ,  G06F13/4068 ,  G11C5/02 ,  G11C7/10 ,  G11C7/1012 ,  G11C7/1021 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/419 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028

Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

Abstract translation: 半导体存储器系统包括第一半导体存储器管芯和第二半导体存储器管芯。 第一半导体存储器管芯包括主数据接口，用于在写操作期间接收输入数据流，并将输入数据流反序列化为第一多个数据流，并且还包括耦合到主数据接口的辅数据接口， 发送第一多个数据流。 第二半导体存储器管芯包括耦合到第一半导体存储器管芯的次级数据接口的次级数据接口，以接收第一多个数据流。

公开(公告)号：US20150085595A1

公开(公告)日：2015-03-26

申请号：US14554904

申请日：2014-11-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent Haukness

IPC: G11C11/406

CPC classification number: G11C11/40611 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C2211/4067 ,  Y02D10/14

Abstract: The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller.

Abstract translation: 本实施例提供一种支持存储设备中的自刷新操作的系统。 在操作期间，系统将存储器设备从自动刷新状态转变，其中存储器控制器将存储器设备的刷新操作控制到自刷新状态，其中存储器设备控制刷新操作。 当存储器件处于自刷新状态时，系统将刷新操作的进程信息从存储器件发送到存储器控制器。 接下来，当从自刷新状态返回到自动刷新状态时，系统使用从存储装置接收到的进度信息来控制存储器控制器的后续操作的顺序。

公开(公告)号：US20150082119A1

公开(公告)日：2015-03-19

申请号：US14475619

申请日：2014-09-03

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Scott C. Best

IPC: H03M13/15 ,  G06F11/10 ,  H03M13/00

CPC classification number: G06F11/1048 ,  H03M13/1525 ,  H03M13/19 ,  H03M13/617

Abstract: A memory system includes a memory module that supports error detection and correction (EDC) in a manner that relieves a memory controller or processor of some or all of the computational burden associated with EDC. individual EDC components perform EDC functions on subsets of the data, and share data between themselves using relatively short, fast interconnections.

Abstract translation: 存储器系统包括以能够缓解存储器控制器或处理器与EDC相关联的一些或全部计算负担的方式支持错误检测和校正（EDC）的存储器模块。 单独的EDC组件在数据子集上执行EDC功能，并使用相对较短，快速的互连在其间共享数据。

公开(公告)号：US20150063433A1

公开(公告)日：2015-03-05

申请号：US14535006

申请日：2014-11-06

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Frederick A. Ware ,  Richard E. Perego

IPC: H04B17/00

CPC classification number: H04B17/11 ,  H04B17/00 ,  H04B17/21 ,  H04L7/0004 ,  H04L7/0016 ,  H04L7/0087 ,  H04L7/043 ,  H04L7/10 ,  H04L27/00

Abstract: A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

公开(公告)号：US20150061065A1

公开(公告)日：2015-03-05

申请号：US14462644

申请日：2014-08-19

Applicant: Rambus Inc.

Inventor： Patrick R. Gill ,  David Geoffrey Stork

IPC: H01L27/146

CPC classification number: H01L27/14625 ,  G02B5/1819 ,  G02B5/1842 ,  H01L27/1462 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14629

Abstract: An array of diffraction-pattern generators employ phase anti-symmetric gratings to projects near-field spatial modulations onto a closely spaced array of photoelements. Each generator in the array of generators produces point-spread functions with spatial frequencies and orientations of interest. The generators are arranged in an irregular mosaic with little or no short-range repetition. Diverse generators are shaped and placed with some irregularity to reduce or eliminate spatially periodic replication of ambiguities to facilitate imaging of nearby scenes.

Abstract translation: 衍射图形发生器阵列采用相位反对称光栅将近场空间调制投影到紧密间隔的光电元件阵列上。 发生器阵列中的每个发生器产生具有空间频率和感兴趣方向的点扩展函数。 发电机布置成不规则的马赛克，很少或没有短距离的重复。 不同的发电机的形状和放置有一些不规则，以减少或消除空间周期性的模糊性复制，以促进附近场景的成像。