公开(公告)号：US5760497A

公开(公告)日：1998-06-02

申请号：US684192

申请日：1996-07-19

Applicant: Luigi Pascucci

Inventor： Luigi Pascucci

IPC: G05F3/24 ,  H02M3/07 ,  H02M3/18

CPC classification number: G05F3/24 ,  H02M3/073

Abstract: A charge pump circuit includes a plurality of voltage boost stages that are mutually parallel-connected between a supply line and an output line. Each of the stages includes first and second charge storing devices in each of which a first terminal is connected to a charge/discharge node and a second terminal is connected to a boost node to switch between a first charge state and a second charge state for transferring a charge to the output line. Each stage also includes an inverter with an input node connected to the boost node related to the first charge storing device and an output node which is connected to the boost node related to the second charge storing device. Further, a first charge transfer diode, which is connected between the charge/discharge node related to the first charge storing device and the output line and a second charge transfer diode, which is connected between the charge/discharge node related to the second charge storing device and the output line are also included in each stage. Each one of the voltage boost stages includes an additional diode that is connected between the charge/discharge node related to the first charge storing device and the output line. The additional diode discharges the first charge storing device when a potential of the output line is lower than a potential, minus the threshold of the additional diode, of the charge/discharge node related to the first charge storing device.

Abstract translation: 电荷泵电路包括在电源线和输出线之间相互并联连接的多个升压级。 每个级包括第一和第二电荷存储装置，其中第一和第二电荷存储装置，其中第一端子连接到充电/放电节点，第二端子连接到升压节点，以在第一充电状态和第二充电状态之间切换以传送 向输出线充电。 每个级还包括具有连接到与第一电荷存储装置相关的升压节点的输入节点的反相器，以及连接到与第二电荷存储装置相关的升压节点的输出节点。 此外，连接在与第一电荷存储装置相关的充电/放电节点和输出线之间的第一电荷转移二极管和连接在与第二电荷存储相关的充电/放电节点之间的第二电荷转移二极管 设备和输出线也包括在每个阶段。 每个升压级包括连接在与第一电荷存储装置相关的充电/放电节点和输出线之间的附加二极管。 当输出线的电位低于与第一电荷存储装置相关的充电/放电节点的电位减去附加二极管的阈值时，附加二极管对第一电荷存储装置进行放电。

公开(公告)号：US5756387A

公开(公告)日：1998-05-26

申请号：US581493

申请日：1995-12-29

Applicant: Flavio Villa ,  Paolo Ferrari

Inventor： Flavio Villa ,  Paolo Ferrari

IPC: H01L21/329 ,  H01L29/866 ,  H01L21/8222

CPC classification number: H01L29/66106 ,  H01L29/866 ,  Y10S438/912 ,  Y10S438/983

Abstract: Zener diode with high stability in time and low noise for integrated circuits and provided in an epitaxial pocket insulated from the rest of a type N epitaxial layer grown on a substrate of type P semiconductor material. In said pocket are included a type N+ cathode region and a type P anode region enclosing it. The cathode region has a peripheral part surrounding a central part extending in the anode region less deeply than the peripheral part.

Abstract translation: 在集成电路的时间上具有高稳定性和低噪声的齐纳二极管，并且提供在与类型P半导体材料的衬底上生长的N型外延层的其余部分绝缘的外延袋中。 在所述口袋中包括N +型阴极区和包围它的P型阳极区。 阴极区域具有围绕在阳极区域延伸的中心部分的周边部分不比周边部分深。

公开(公告)号：US5748528A

公开(公告)日：1998-05-05

申请号：US642813

申请日：1996-05-03

Applicant: Giovanni Campardo ,  Lorenzo Bedarida ,  Giuseppe Fusillo ,  Andrea Silvagni

Inventor： Giovanni Campardo ,  Lorenzo Bedarida ,  Giuseppe Fusillo ,  Andrea Silvagni

IPC: G11C17/00 ,  G11C7/18 ,  G11C8/10 ,  G11C8/12 ,  G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C16/10 ,  G11C7/18 ,  G11C8/10 ,  G11C8/12 ,  G11C2216/22

Abstract: A memory device having a memory array, a row decoding unit, a column decoding unit, and a control unit; the memory array presents global bit lines extending along the whole of the array and connected to respective local bit lines, one for each of the sectors; a switch is provided between the global bit lines and each respective local bit line to selectively connect a selected global bit line and only one of the associated local bit lines; and the switches are controlled by local decoding units over control lines, to address the sectors independently and so perform operations (read, erase, write) simultaneously in two different sectors in different rows and columns.

Abstract translation: 具有存储器阵列，行解码单元，列解码单元和控制单元的存储器件; 存储器阵列呈现沿整个阵列延伸并连接到相应的局部位线的全局位线，每个扇区一个; 在全局位线和每个相应的局部位线之间提供开关以选择性地连接所选择的全局位线和仅一个相关联的局部位线; 并且开关由控制线上的本地解码单元控制，以独立地寻址扇区，并且因此在不同行和列中的两个不同扇区中同时执行操作（读取，擦除，写入）。

公开(公告)号：US5748128A

公开(公告)日：1998-05-05

申请号：US645457

申请日：1996-05-13

Applicant: Melchiorre Bruccoleri ,  Marco Demicheli ,  Giuseppe Patti ,  Valerio Pisati

Inventor： Melchiorre Bruccoleri ,  Marco Demicheli ,  Giuseppe Patti ,  Valerio Pisati

IPC: H03M1/68 ,  G06J1/00 ,  H03M1/66 ,  H03M1/78 ,  H03M1/16

CPC classification number: H03M1/664 ,  G06J1/00 ,  H03M1/785

Abstract: A digital/analog quadratic converter (DACQ) composed by a pair of linear converters connected in cascade has a direct coupling of the output node of the first converter (DAC1) with a node of a R-2R type resistive network of the second converter (DAC2) corresponding to the LSB stage of the R-2R type resistive network. High impedance nodes, notably the input node of the second linear converter, are advantageously eliminated from the "current path" thus markedly reducing the problems of relatively long settling times of high impedance nodes (having intrinsically large parasitic capacitances associated therewith). The peculiar architecture of the quadratic converter provides also for a remarkable simplification of the circuit.

Abstract translation: 由串联连接的一对线性转换器组成的数字/模拟二次转换器（DACQ）具有第一转换器（DAC1）的输出节点与第二转换器的R-2R型电阻网络的节点的直接耦合 DAC2）对应于R-2R型电阻网络的LSB级。 有利地，从“电流路径”消除高阻抗节点，特别是第二线性转换器的输入节点，从而显着地减少了高阻抗节点（具有与其相关的本质上大的寄生电容）的较长建立时间的问题。 二次转换器的独特结构也为电路的显着简化提供了依据。

公开(公告)号：US5747975A

公开(公告)日：1998-05-05

申请号：US408014

申请日：1995-03-21

Applicant: Francesco Colandrea ,  Vanni Poletto

Inventor： Francesco Colandrea ,  Vanni Poletto

IPC: H03K17/08 ,  H03K17/082 ,  H03K17/567 ,  H03K17/687 ,  G05F1/569 ,  H02H7/00

CPC classification number: H03K17/0822

Abstract: The circuit includes two regulating loops connected in parallel to each other. A slow regulating loop presents a lower first intervention threshold, and a fast regulating loop has a higher second intervention threshold. The slow regulating loop is low-gain and frequency-stable for accurately controlling the maximum value of the current supplied by the driver in the event of slow overloads or transient states. In the event of rapid overloads, the current supply increases rapidly and the fast regulating loop is turned on to rapidly discharge the parasitic capacitance of the driver.

Abstract translation: 该电路包括彼此并联连接的两个调节回路。 缓慢的调节回路具有较低的第一干预阈值，并且快速调节回路具有较高的第二干预阈值。 缓慢调节回路是低增益和频率稳定的，用于在发生缓慢的过载或瞬态时精确控制由驾驶员提供的电流的最大值。 在快速过载的情况下，电流迅速增加，快速调节环路导通，迅速放电驱动器的寄生电容。

公开(公告)号：US5745352A

公开(公告)日：1998-04-28

申请号：US772303

申请日：1996-12-23

Applicant: Paolo Sandri ,  Maria Rosa Borghi ,  Luca Rigazio

Inventor： Paolo Sandri ,  Maria Rosa Borghi ,  Luca Rigazio

IPC: H02M3/156 ,  H02M1/12 ,  G05F1/10

CPC classification number: H02M3/156 ,  H02M2001/0032 ,  Y02B70/16

Abstract: Switching losses in a DC-to-DC converter idling in a pulse-skipping mode are reduced by inhibiting any intervening turn-off command by a PWM control loop of the converter for as long as the current through the inductor of the converter remains below a minimum threshold value set by a dedicated comparator. The method is implemented by employing a comparator with a certain hysteresis and by logically masking the switching to a logic "0" of a high frequency clock (switching) signal of the converter for the entire period of time the current in the inductor remains below the minimum threshold.

Abstract translation: 只要通过转换器的电感器的电流保持低于1，则通过抑制转换器的PWM控制环的任何中间关断命令来减少在脉冲跳跃模式中空转的DC-DC转换器中的开关损耗 由专用比较器设置的最小阈值。 该方法通过采用具有一定滞后的比较器来实现，并且通过在电感器中的电流保持在低于该值的整个时间段内逻辑地屏蔽转换器的高频时钟（切换）信号的逻辑“0” 最小门槛。

公开(公告)号：US5734287A

公开(公告)日：1998-03-31

申请号：US545165

申请日：1995-10-19

Applicant: Pietro Consiglio ,  Carlo Antonini

Inventor： Pietro Consiglio ,  Carlo Antonini

IPC: H03G5/16 ,  H02J7/00 ,  H03F1/32 ,  H04M1/60 ,  H03K5/08

CPC classification number: H02J7/0021 ,  H03F1/3217

Abstract: Distortion control in a push-pull output stage of a speech amplifier of a telephone powered through the telephone line is more effectively and advantageously implemented by independently sensing an eventual state of saturation reached by any of the two output transistors of the amplifier, summing the current signals representative of the sensed state of saturation of either or both output transistors, integrating the resulting sum current signal to produce a DC signal and using the DC signal for activating an AGC loop. The DC signal indiscriminately accounts for any cause of saturation, though virtually representing the level of the amplified AC signal. Distortion may be controlled without penalizing output voltage swing and power consumption.

Abstract translation: 通过电话线供电的电话的语音放大器的推挽输出级中的失真控制通过独立地感测由放大器的两个输出晶体管中的任一个达到的最终饱和状态而被更有效地和有利地实现， 表示感测到的任一个或两个输出晶体管的饱和状态的信号，积分所得到的和电流信号以产生DC信号，并使用DC信号来激活AGC环路。 直流信号不加区分地解释了任何饱和原因，尽管实际上代表了放大的交流信号的电平。 可以控制失真，而不会影响输出电压摆幅和功耗。

公开(公告)号：US5732012A

公开(公告)日：1998-03-24

申请号：US210595

申请日：1994-03-17

Applicant: Paolo Cappelletti ,  Silvia Lucherini ,  Bruno Vajana

Inventor： Paolo Cappelletti ,  Silvia Lucherini ,  Bruno Vajana

IPC: H01L21/8247 ,  H01L21/8246 ,  H01L27/112 ,  H01L27/115 ,  G11C17/12

CPC classification number: H01L27/11253 ,  H01L27/112 ,  H01L27/1126 ,  H01L27/11266

Abstract: A ROM cell array in which the drains are more lightly doped than the sources. This reduces the worst-case capacitance seen by the bitlines, and consequently reduces the access time of the memory.

Abstract translation: 一个ROM单元阵列，其中漏极比源轻掺杂。 这减少了位线所看到的最坏情况电容，从而减少了存储器的访问时间。

公开(公告)号：US5729492A

公开(公告)日：1998-03-17

申请号：US639192

申请日：1996-04-26

Applicant: Giovanni Campardo

Inventor： Giovanni Campardo

IPC: G11C17/00 ,  G11C16/06 ,  G11C16/28

CPC classification number: G11C16/28

Abstract: A sense amplifier circuit for a semiconductor memory device comprises a first current/voltage converter for convening a current of a memory cell to be read into a voltage signal, a second current/voltage converter for converting a reference current into a reference voltage signal, and a voltage comparator for comparing the voltage signal with the reference voltage signal. The sense amplifier circuit comprises a capacitive decoupler for decoupling the voltage signal from the comparator, and circuitry for providing the capacitive decoupler with an electric charge suitable for compensating an offset voltage introduced in the voltage signal by an offset current superimposed on the current of the memory cell to be read.

Abstract translation: 一种用于半导体存储器件的读出放大器电路包括用于将待读取的存储单元的电流转换为电压信号的第一电流/电压转换器，将参考电流转换为参考电压信号的第二电流/电压转换器，以及 电压比较器，用于将电压信号与参考电压信号进行比较。 感测放大器电路包括用于去耦电压信号与比较器的电容去耦器，以及电路，用于向电容解耦器提供适合于通过叠加在存储器电流上的偏置电流补偿电压信号中引入的偏移电压的电荷 单元格被读取。

公开(公告)号：US5729490A

公开(公告)日：1998-03-17

申请号：US690059

申请日：1996-07-31

Applicant: Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

Inventor： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

IPC: G11C11/56 ,  G11C7/00

CPC classification number: G11C11/5642 ,  G11C11/5621 ,  G11C2211/5632 ,  G11C2211/5633

Abstract: A method for sensing multiple-levels non-volatile memory cells which can take one programming level among a plurality of m=2.sup.n (n>=Z) different programming levels, provides for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a discrete set of m distinct cell current values, each cell current value corresponding to one of said programming levels. The sensing method also provides for: simultaneously comparing the cell current with a prescribed number of reference currents having values comprised between a minimum value and a maximum value of said discrete set of m cell current values and dividing said discrete set of m cell current values in a plurality of sub-sets of cell current values, for determining the sub-set of cell current values to which the cell current belongs; repeating step (a) for the sub-set of cell current values to which the cell current belongs, until the sub-set of cell current values to which the cell current belongs comprises only one cell current value, which is the value of the current of the memory cell to be sensed.

Abstract translation: 用于感测可以在多个m = 2n（n> = Z）个不同编程级别中采取一个编程电平的多级非易失性存储器单元的方法提供了在预定条件下偏置要感测的存储器单元，因此 存储器单元以具有m个不同单元电流值的离散集合的值吸收单元电流，每个单元电流值对应于所述编程电平之一。 感测方法还提供：同时将电池电流与规定数量的参考电流进行比较，所述规定数量的参考电流具有包括在所述离散的一组m个电池电流值的最小值和最大值之间的值，并且将所述离散的一组m个电池电流值 多个子单元电流子集，用于确定单元电流所属的单元电流值的子集; 对于单元电流所属的单元电流值的子集重复步骤（a），直到单元电流所属的单元电流值的子集仅包括一个单元电流值，该单元电流值是电流值 的待读取的存储单元。