公开(公告)号：US10128295B2

公开(公告)日：2018-11-13

申请号：US15866995

申请日：2018-01-10

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien Lagrasta ,  Delia Ristoiu ,  Jean-Pierre Oddou ,  Cécile Jenny

IPC: H01L27/146

Abstract: A semiconductor substrate includes a photodiode region, a charge storage region electrically coupled to the photodiode region and a capacitive deep trench isolation (CDTI) structure including a conductive region positioned between the photodiode region and the charge storage region. A contact etch stop layer overlies the semiconductor substrate and a premetallization dielectric layer overlies the contact etch stop layer. A first trench, filled with a metal material, extends through the premetallization dielectric layer and bottoms out at or in the contact etch stop layer. A second trench, also filled with the metal material, extends through the premetallization dielectric layer and the contact etch stop layer and bottoms out at or in the conductive region of the CDTI structure. The metal filled first trench forms an optical shield between the photodiode region and the charge storage region. The metal filled second trench forms a contact for biasing the CDTI structure.

公开(公告)号：US10127966B2

公开(公告)日：2018-11-13

申请号：US15389751

申请日：2016-12-23

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Antonino Conte ,  Enrico Castaldo ,  Raul Andres Bianchi ,  Francesco La Rosa

IPC: G11C11/24 ,  G04F10/10

Abstract: A reading circuit for a charge-retention circuit stage is provided with a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The reading circuit further has an operational amplifier having a first input terminal that is coupled to the floating node and receives a reading voltage, a second input terminal receives a reference voltage, and an output terminal on which it supplies an output voltage, the value of which is a function of the comparison between the reading voltage and the reference voltage and indicative of a residual charge in the storage capacitor. A shifting stage shifts the value of the reading voltage of the floating node, before the comparison is made between the reading voltage and the reference voltage for supplying the output voltage.

公开(公告)号：US10126499B2

公开(公告)日：2018-11-13

申请号：US14754994

申请日：2015-06-30

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Jean-Robert Manouvrier ,  Jean-Francois Carpentier ,  Patrick Lemaitre

IPC: G02B6/34 ,  G02B6/124 ,  G02B6/30 ,  G02B6/293

Abstract: An electro-optic device may include a photonic chip having an optical grating coupler at a surface. The optical grating coupler may include a first semiconductor layer having a first base and first fingers extending outwardly from the first base. The optical grating coupler may include a second semiconductor layer having a second base and second fingers extending outwardly from the second base and being interdigitated with the first fingers to define semiconductor junction areas, with the first and second fingers having a non-uniform width. The electro-optic device may include a circuit coupled to the optical grating coupler and configured to bias the semiconductor junction areas and change one or more optical characteristics of the optical grating coupler.

公开(公告)号：US20180323237A1

公开(公告)日：2018-11-08

申请号：US15968474

申请日：2018-05-01

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pierre MORIN ,  Philippe BRUN ,  Laurent-Luc CHAPELON

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L27/2463 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/5329 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

Abstract: A phase-change memory includes a strip of phase-change material that is coated with a conductive strip and surrounded by an insulator. The strip of phase-change material has a lower face in contact with tips of a resistive element. A connection network composed of several levels of metallization coupled with one another by conducting vias is provided above the conductive strip. At least one element of a lower level of the metallization is in direct contact with the upper surface of the conductive strip.

公开(公告)号：US20180301625A1

公开(公告)日：2018-10-18

申请号：US15953921

申请日：2018-04-16

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics S.r.l.

Inventor： Pierre MORIN ,  Michel HAOND ,  Paola ZULIANI

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/126 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1608

Abstract: A phase change memory includes an L-shaped resistive element having a first part that extends between a layer of phase change material and an upper end of a conductive via and a second part that rests at least partially on the upper end of the conductive via and may further extend beyond a peripheral edge of the conductive via. The upper part of the conductive via is surrounded by an insulating material that is not likely to adversely react with the metal material of the resistive element.

公开(公告)号：US20180286878A1

公开(公告)日：2018-10-04

申请号：US15995452

申请日：2018-06-01

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Stephane Zoll ,  Philippe Garnier

IPC: H01L27/11539 ,  H01L27/11521 ,  H01L21/28 ,  H01L29/788

Abstract: Active areas of memory cells and active areas of transistors are delimited in an upper portion of a wafer. Floating gates are formed on active areas of the memory cells. A silicon oxide-nitride-oxide tri-layer is then deposited over the wafer and a protection layer is deposited over the silicon oxide-nitride-oxide tri-layer. Portions of the protection layer and tri-layer located over the active areas of transistors are removed. Dielectric layers are formed over the wafer and selectively removed from covering the non-removed portions of the protection layer and tri-layer. A memory cell gate is then formed over the non-removed portions of the protection layer and tri-layer and a transistor gate is then formed over the non-removed portions of the dielectric layers.

公开(公告)号：US20180286763A1

公开(公告)日：2018-10-04

申请号：US15942540

申请日：2018-04-01

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Loic GABEN

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/48 ,  H01L23/52 ,  H01L27/088

Abstract: A strip made of a semiconductor material is formed over a substrate. Longitudinal portions of the strip having a same length are covered with sacrificial gates made of an insulating material and spaced apart from each other. Non-covered portions of the strip are doped to form source/drain regions. An insulating layer followed by a layer of a temporary material is then deposited. Certain ones of the sacrificial gates are left in place. Certain other ones of the sacrificial gates are replaced by a metal gate structure. The temporary material is then replaced with a conductive material to form contacts to the source/drain regions.

公开(公告)号：US10090355B2

公开(公告)日：2018-10-02

申请号：US15266345

申请日：2016-09-15

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： François Roy ,  Frédéric Lalanne ,  Pierre Emmanuel Marie Malinge

IPC: H01L27/00 ,  H01L27/146 ,  H04N5/378

Abstract: An image sensor device may include an array of image sensing pixels arranged in rows and columns. Each image sensing pixel may include an image sensing photodiode, a first source follower transistor coupled to the image sensing photodiode, and a switch coupled to the image sensing photodiode. Each image sensor device may include a second source follower transistor coupled to the switch, and a row selection transistor coupled to the first and second source follower transistors.

公开(公告)号：US20180277659A1

公开(公告)日：2018-09-27

申请号：US15707258

申请日：2017-09-18

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Alexis Gauthier ,  Guillaume C. Ribes

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/12 ,  H01L49/00

CPC classification number: H01L29/66666 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28008 ,  H01L21/308 ,  H01L29/127 ,  H01L29/42376 ,  H01L29/7827 ,  H01L49/006

Abstract: A vertical transistor includes two portions of a gate conductor that extend within a layer of insulator. An opening extending through the later of insulator includes source, channel and drain regions form by epitaxy operations. A thickness of the portions of the gate conductor decreases in the vicinity of the channel region.

公开(公告)号：US10075102B2

公开(公告)日：2018-09-11

申请号：US15139151

申请日：2016-04-26

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Arthur Arnaud ,  Jihane Boughaleb ,  Stephane Monfray ,  Thomas Skotnicki

IPC: H01L41/113 ,  H02N2/18 ,  H02N3/00 ,  F03G7/06

CPC classification number: H02N2/18 ,  F03G7/06 ,  H01L41/1134 ,  H02N3/00

Abstract: A system for converting thermal energy into electrical power includes a temperature-sensitive element held in a frame by its two ends between a heat source and a cold source producing a thermal gradient. A piezoelectric element is positioned between the frame and at least one end of the temperature-sensitive element. The temperature-sensitive element is configured to deform cyclically between two states under the action of the thermal gradient. With each cyclic deformation, a stress is applied to the piezoelectric element via the one end.