公开(公告)号：US20220336657A1

公开(公告)日：2022-10-20

申请号：US17620952

申请日：2020-05-26

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Zhili ZHANG ,  Jingchuan ZHAO ,  Sen ZHANG

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/40

Abstract: A laterally diffused metal-oxide-semiconductor (LDMOS) device and a method of manufacturing the LDMOS device are disclosed. The method includes: obtaining a substrate with a drift region formed thereon, the drift region having a first conductivity type and disposed on the substrate of a second conductivity type; etching the drift region to form therein a sinking structure, the sinking structure includes at least one of an implanting groove and an implanting hole; implanting ions of the second conductivity type at the bottom of the sinking structure; forming a buried layer of the second conductivity type by causing diffusion of the ions of the second conductivity type using a thermal treatment; and filling an electrical property modification material into the sinking structure, the electrical property modification material differs from the material of the drift region.

公开(公告)号：US11315824B2

公开(公告)日：2022-04-26

申请号：US16483081

申请日：2018-07-03

Applicant: CSMC Technologies FAB2 Co., Ltd.

Inventor： Shukun Qi

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/32 ,  H01L21/761 ,  H01L29/06

Abstract: A method for manufacturing a trench isolation structure comprising forming a shallow trench having a wider upper section and a narrower lower section in a wafer surface, removing part of the silicon oxide by etching, forming a silicon oxide corner structure at a corner at a top corner of the shallow trench by thermal oxidation, depositing silicon nitride on the wafer surface to cover surfaces of the shallow trench silicon oxide and the silicon oxide corner structure, dry etching the silicon nitride on the shallow trench silicon oxide surface thereby forming masking silicon nitride residues extending into the trench, etching downwards to form a deep trench, forming silicon oxide layers on a side wall and the bottom of the deep trench, depositing polycrystalline silicon in the shallow and deep trenches, removing the silicon nitride, and forming silicon oxide in the shallow trench to cover the polycrystalline silicon.

公开(公告)号：US11309406B2

公开(公告)日：2022-04-19

申请号：US16770362

申请日：2018-12-05

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Nailong He ,  Sen Zhang ,  Guangsheng Zhang ,  Yun Lan

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/417 ,  H01L21/033 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423

Abstract: A manufacturing method of an LDMOS device comprises: obtaining a wafer formed with a doped region having a first conductivity type, wherein a top buried layer is formed inside the doped region having the first conductivity type, and a field oxide insulation layer structure is formed on the top buried layer; disposing a trench on the doped region having the first conductivity type, wherein the trench extends to the top buried layer and the field oxide insulation layer structure such that a portion of the top buried layer is removed; injecting an ion of a second conductivity type to form a well region below the trench; and forming a doped source region in the well region. The first conductivity type and the second conductivity type are opposite conductivity types.

公开(公告)号：US20220077865A1

公开(公告)日：2022-03-10

申请号：US17419548

申请日：2019-12-23

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Chen LI ,  Hao WANG

IPC: H03M1/00 ,  H03M1/06

Abstract: An analog-to-digital converter and a clock generation circuit thereof are provided. The clock generation circuit comprises cascaded clock generation modules. The clock generation module at each stage is configured to generate a corresponding internal clock signal, and each stage of the clock generation module comprises a delay module and a logic gate module. The second input end of the N-th stage of the logic gate module is connected to the output end of the previous stage of the logic gate module, and the output end of the logic gate module is configured to output an internal clock, so that each stage of the clock generation module can generate one internal clock signal.

公开(公告)号：US20220069718A1

公开(公告)日：2022-03-03

申请号：US17420866

申请日：2020-06-19

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shen XU ,  Minggang CHEN ,  Wanqing YANG ,  Dejin WANG ,  Rui JIANG ,  Weifeng SUN ,  Longxing SHI

IPC: H02M3/335 ,  H02M1/38

Abstract: Disclosed are a system and method for controlling an active clamp flyback (ACF) converter. The system includes: a drive module configured to control turning-on or turning-off of a main switching transistor SL and a clamp switching transistor SH; a main switching transistor voltage sampling circuit configured to sample a voltage drop between an input terminal and an output terminal of the main switching transistor SL; a first comparator connected to the main switching transistor voltage sampling circuit and configured to determine whether a sampled first sampling voltage is a positive voltage or a negative voltage; and a dead time calculation module configured to adjust, according to an output of the first comparator and a main switching transistor control signal DUTYL of a current cycle, a clamp switching transistor control signal DUTYH of next cycle outputted by the drive module.

公开(公告)号：US11127840B2

公开(公告)日：2021-09-21

申请号：US16481576

申请日：2018-07-03

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shukun Qi ,  Guipeng Sun

IPC: H01L21/763 ,  H01L21/473 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/762

Abstract: Disclosed is a method for manufacturing an isolation structure for LDMOS, the method comprising: forming a first groove on the surface of a wafer; filling the first groove with silicon oxide; removing part of the surface of the silicon oxide within the first groove by means of etching; forming a silicon oxide corner structure at the corner of the top of the first groove by means of thermal oxidation; depositing a nitrogen-containing compound on the surface of the wafer to cover the surface of the silicon oxide within the first groove and the surface of the silicon oxide corner structure; dry-etching the nitrogen-containing compound to remove the nitrogen-containing compound from the surface of the silicon oxide within the first groove, and thereby forming a nitrogen-containing compound side wall residue; with the nitrogen-containing compound side wall residue as a mask, continuing to etch downwards to form a second groove; forming a silicon oxide layer on the side wall and the bottom of the second groove; removing the nitrogen-containing compound side wall residue; and filling the first groove and the second groove with silicon oxide.

公开(公告)号：US20210167190A1

公开(公告)日：2021-06-03

申请号：US16771168

申请日：2018-11-13

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun JIN ,  Guipeng SUN

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/78

Abstract: A semiconductor device, and a manufacturing method thereof. The method includes: providing a semiconductor substrate provided with a body region, a gate dielectric layer, and a field oxide layer, formed on the semiconductor substrate; forming a gate polycrystalline, the gate polycrystalline covering the gate dielectric layer and the field oxide layer and exposing at least one portion of the field oxide layer; forming a drift region in the semiconductor substrate by ion implantation using a drift region masking layer as a mask, removing the exposed portion of the field oxide layer by further using the drift region masking layer as the mask to form a first field oxide self-aligned with the gate polycrystalline; forming a source region in the body region, and forming a drain region in the drift region; forming a second field oxide on the semiconductor substrate; and forming a second field plate on the second field oxide.

公开(公告)号：US20210043623A1

公开(公告)日：2021-02-11

申请号：US16980368

申请日：2019-03-05

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Jun Sun

IPC: H01L27/07 ,  H01L29/78 ,  H01L29/08

Abstract: An anti-static metal oxide semiconductor field effect transistor structure includes an anti-static body structure and a slave metal oxide semiconductor field effect transistor, the anti-static body structure includes: a main metal oxide semiconductor field effect transistor; a first silicon controlled rectifier, an anode thereof being connected to a drain of the main metal oxide semiconductor field effect transistor, a cathode and a control electrode thereof being connected to a source of the main metal oxide semiconductor field effect transistor; and a second silicon controlled rectifier, an anode thereof being connected to the drain of the main metal oxide semiconductor field effect transistor, a cathode thereof being connected to a gate of the main metal oxide semiconductor field effect transistor, a control electrode thereof being connected to the source or the gate of the main metal oxide semiconductor field effect transistor.

公开(公告)号：US20210028289A1

公开(公告)日：2021-01-28

申请号：US17041980

申请日：2019-03-27

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Dong FANG ,  Zheng BIAN

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/40 ,  H01L21/285

Abstract: A method for manufacturing a trenched split-gate device, comprising: etching a semiconductor substrate to form a trench (120); depositing an oxide in the trench to form a floating-gate oxide layer in which the floating-gate oxide layer gradually thickens from top to bottom along a side wall of the trench, and a thickness of the floating gate oxide layer at a lower part of the side wall of the trench is the same as that of the floating gate oxide layer at a bottom of the trench; depositing polysilicon into the trench to form a floating-gate polysilicon layer (123); growing an insulation medium on an upper surface of the floating-gate polysilicon layer to form an isolation layer (124); and forming a control gate on the isolation layer in the trench.

公开(公告)号：US10816893B2

公开(公告)日：2020-10-27

申请号：US16305308

申请日：2017-05-26

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Jinyin Wan

IPC: G06F30/00 ,  G06F30/20 ,  G06F30/398 ,  G03F1/36

Abstract: A method for correction of an optical proximity effect, comprising: parsing and dividing the periphery of a design pattern to obtain segments to process; for a segment having a corner comprising a segment side (101) and an adjacent side (102) forming a corner relation with the segment side, setting a target point according to the following principle: when the length of the adjacent side (102) is greater than a preset length, the target point is set at the location of the outer end point (104) of the segment side; when the length of the adjacent side (102) is less than or equal to the preset length, the target point is set between the vertex (103) of the corner and the outer end point (104) of the segment side, and the less the length of the adjacent side (102), the further the target point from the location of the outer end point (104); and adjusting, according to a simulation difference of the target point, the design pattern until it conforms to a design target.