公开(公告)号：US20130026646A1

公开(公告)日：2013-01-31

申请号：US13193991

申请日：2011-07-29

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Alvin J. Joseph

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Alvin J. Joseph

IPC: H01L21/28 ,  G06F17/50 ,  H01L23/48 ,  H01L21/22 ,  H01L21/265

CPC classification number: H01L21/76898 ,  H01L21/26586 ,  H01L29/732

Abstract: A method for forming passivated through wafer vias, passivated through wafer via structures, and passivated through wafer via design structures. The method includes: forming a through wafer via in a semiconductor substrate, the through wafer via comprising an electrical conductor extending from a top of the semiconductor substrate to a bottom surface of the semiconductor substrate; and forming a doped layer abutting all sidewalls of the electrical conductor, the doped layer of a same dopant type as the semiconductor substrate, the concentration of dopant in the doped layer greater than the concentration of dopant in the semiconductor substrate, the doped layer intervening between the electrical conductor and the semiconductor substrate.

Abstract translation: 用于形成钝化的晶片通孔的方法，通过晶片通孔结构钝化，并通过设计结构钝化通过晶片。 该方法包括：在半导体衬底中形成贯穿晶片通孔，所述贯通晶片通孔包括从半导体衬底的顶部延伸到半导体衬底的底表面的电导体; 并且形成邻接电导体的所有侧壁的掺杂层，与半导体衬底相同的掺杂剂类型的掺杂层，掺杂层中掺杂剂的浓度大于半导体衬底中掺杂剂的浓度，掺杂层介于 电导体和半导体衬底。

公开(公告)号：US08233070B2

公开(公告)日：2012-07-31

申请号：US12553457

申请日：2009-09-03

Applicant: John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Charles F. Musante

Inventor： John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Charles F. Musante

IPC: H04N3/14

CPC classification number: H04N5/37452 ,  H01L27/14609 ,  H04N5/35581 ,  H04N5/3575

Abstract: A pixel sensor cell including a column circuit, a design structure for fabricating the pixel sensor cell including the column circuit and a method for operating the pixel sensor cell including the column circuit are predicated upon the measurement of multiple reference data point and signal data point pairs from a floating diffusion at a variable capacitance. The variable capacitance is provided by excluding or including a transfer gate transistor capacitance in addition to a floating diffusion capacitance. Such a variable capacitance provides variable dynamic ranges for the pixel sensor cell including the column circuit.

Abstract translation: 包括列电路的像素传感器单元，用于制造包括列电路的像素传感器单元的设计结构和用于操作包括列电路的像素传感器单元的方法基于多个参考数据点和信号数据点对的测量 从可变电容的浮动扩散。 通过排除或包括传输栅极晶体管电容以及浮动扩散电容来提供可变电容。 这种可变电容为包括列电路的像素传感器单元提供了可变的动态范围。

公开(公告)号：US20120122261A1

公开(公告)日：2012-05-17

申请号：US13288686

申请日：2011-11-03

Applicant: James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Dale J. Pearson ,  Dennis L. Rogers

Inventor： James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Dale J. Pearson ,  Dennis L. Rogers

IPC: H01L31/18

CPC classification number: H01L27/14643 ,  H01L27/1463 ,  H01L27/14689 ,  H01L31/035281

Abstract: A method for manufacturing a pixel sensor cell that includes a photosensitive element having a non-laterally disposed charge collection region. The method includes forming a trench recess in a substrate of a first conductivity type material, and filling the trench recess with a material having second conductivity type material. The second conductivity type material is then diffused out of the filled trench material to the substrate region surrounding the trench to form the non-laterally disposed charge collection region. The filled trench material is removed to provide a trench recess, and the trench recess is filled with a material having a first conductivity type material. A surface implant layer is formed at either side of the trench having a first conductivity type material. A collection region of a trench-type photosensitive element is formed of the outdiffused second conductivity type material and is isolated from the substrate surface.

Abstract translation: 一种制造像素传感器单元的方法，该像素传感器单元包括具有非横向放置的电荷收集区域的感光元件。 该方法包括在第一导电类型材料的衬底中形成沟槽凹槽，并用具有第二导电类型材料的材料填充沟槽凹槽。 然后将第二导电类型材料从填充的沟槽材料扩散到围绕沟槽的衬底区域，以形成非横向布置的电荷收集区域。 去除填充的沟槽材料以提供沟槽凹槽，并且用具有第一导电类型材料的材料填充沟槽凹槽。 表面注入层形成在具有第一导电类型材料的沟槽的任一侧。 沟槽型感光元件的收集区域由向外扩散的第二导电型材料形成，并与衬底表面隔离。

公开(公告)号：US08168474B1

公开(公告)日：2012-05-01

申请号：US12987402

申请日：2011-01-10

Applicant: James W. Adkisson ,  Panglijen Candra ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Yen L. Lim

Inventor： James W. Adkisson ,  Panglijen Candra ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Yen L. Lim

IPC: H01L21/00

CPC classification number: H01L21/78 ,  H01L21/76898

Abstract: Systems and methods simultaneously form first openings and second openings in a substrate. The first openings are formed smaller than the second openings. The method also simultaneously forms a first material in the first openings and the second openings. The first material fills the first openings, and the first material lines the second openings. The method forms a second material different than the first material in the second openings. The second material fills the second openings. The method forms a plurality of integrated circuit structures over the first material and the second material within the second openings. The method applies mechanical stress to the substrate to cause the substrate to split along the first openings.

Abstract translation: 系统和方法同时在衬底中形成第一开口和第二开口。 第一开口形成为小于第二开口。 该方法还同时在第一开口和第二开口中形成第一材料。 第一材料填充第一开口，第一材料将第二开口排列。 该方法形成与第二开口中的第一材料不同的第二材料。 第二材料填充第二开口。 该方法在第二开口内的第一材料和第二材料上形成多个集成电路结构。 该方法对基板施加机械应力以使基板沿着第一开口分开。

公开(公告)号：US20120038811A1

公开(公告)日：2012-02-16

申请号：US13283819

申请日：2011-10-28

Applicant: John J. Ellis-Monaghan ,  Mark D. Jaffe

Inventor： John J. Ellis-Monaghan ,  Mark D. Jaffe

IPC: H04N5/335 ,  H01L27/148

CPC classification number: H04N5/361 ,  H04N5/359

Abstract: The image qualify of an image frame from a CMOS image sensor array operated in global shutter mode may be enhanced by dispersing or randomizing the noise introduced by leakage currents from floating drains among the rows of the image frame. Further, the image quality may be improved by accounting for time dependent changes in the output of dark pixels in dark pixel rows or dark pixel columns. In addition, voltage and time dependent changes in the output of dark pixels may also be measured to provide an accurate estimate of the noise introduced to the charge held in the floating drains. Such methods may be employed individually or in combination to improve the quality of the image.

Abstract translation: 来自在全球快门模式下操作的CMOS图像传感器阵列的图像帧的图像限定可以通过将来自浮动排水口的泄漏电流引入的噪声分散或随机化在图像帧的行中来增强。 此外，通过考虑暗像素行或暗像素列中的暗像素的输出中的时间依赖性变化，可以提高图像质量。 此外，还可以测量暗像素的输出中的电压和时间相关的变化，以提供引入到浮动排水管中的电荷的噪声的准确估计。 这样的方法可以单独使用或组合使用以提高图像的质量。

公开(公告)号：US20110279399A1

公开(公告)日：2011-11-17

申请号：US12779994

申请日：2010-05-14

Applicant: Brent A. Anderson ,  Mark D. Jaffe ,  Jed H. Rankin

Inventor： Brent A. Anderson ,  Mark D. Jaffe ,  Jed H. Rankin

IPC: G06F3/045 ,  G06F3/041 ,  G06F3/042 ,  G09G5/00

CPC classification number: G06F3/042 ,  G06F3/041 ,  G06F3/0421 ,  G06F3/044 ,  G06F2203/04109

Abstract: Disclosed herein are embodiments of an interface device (e.g., a display, touchpad, touchscreen display, etc.) with integrated power collection functions. In one embodiment, a solar cell or solar cell array can be located within a substrate at a first surface and an array of interface elements can also be located within the substrate at the first surface such that portions of the solar cell(s) laterally surround the individual interface elements or groups thereof. In another embodiment, a solar cell or solar cell array can be located within the substrate at a first surface and an array of interface elements can be located within the substrate at a second surface opposite the first surface (i.e., opposite the solar cell or solar cell array). In yet another embodiment, an array of diodes, which can function as either solar cells or sensing elements, can be within a substrate at a first surface and can be wired to allow for selective operation in either a power collection mode or sensing mode.

Abstract translation: 这里公开了具有集成的功率收集功能的接口设备（例如，显示器，触摸板，触摸屏显示器等）的实施例。 在一个实施例中，太阳能电池或太阳能电池阵列可以位于第一表面的衬底内，并且界面元件阵列也可以位于第一表面的衬底内，使得太阳能电池的一部分横向包围 各个接口元件或其组合。 在另一个实施例中，太阳能电池或太阳能电池阵列可以位于第一表面的衬底内，并且界面元件的阵列可以位于衬底内的与第一表面相对的第二表面（即，与太阳能电池或太阳能 单元格阵列）。 在另一个实施例中，可以用作太阳能电池或感测元件的二极管阵列可以在第一表面的衬底内，并且可以被布线以允许在电力收集模式或感测模式中的选择性操作。

公开(公告)号：US20100097511A1

公开(公告)日：2010-04-22

申请号：US12641589

申请日：2009-12-18

Applicant: James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Charles F. Musante ,  Richard J. Rassel

Inventor： James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Charles F. Musante ,  Richard J. Rassel

IPC: H04N5/335 ,  G06F17/50

CPC classification number: H04N5/361 ,  G06F17/5063 ,  H04N5/359 ,  H04N5/3745

Abstract: A global shutter compatible pixel circuit comprising a reset gate (RG) transistor is provided in which a dynamic voltage is applied to the drain of the reset gate transistor in order to reduce a floating diffusion (FD) leakage therethrough during signal hold time. The drain voltage of the reset gate transistor is held at a lower voltage than a circuit supply voltage to minimize the off-state leakage through the RG transistor, thus reducing the change in the voltage at the floating diffusion during the signal hold time. In addition, a design structure for such a circuit providing a dynamic voltage to the drain of a reset gate of a pixel circuit is also provided.

Abstract translation: 提供了包括复位栅极（RG）晶体管的全局快门兼容像素电路，其中动态电压被施加到复位栅极晶体管的漏极，以便减少在信号保持时间期间通过其的浮动扩散（FD）泄漏。 复位栅极晶体管的漏极电压保持在比电路电源电压更低的电压，以最小化通过RG晶体管的截止状态泄漏，从而减少信号保持时间期间浮动扩散时的电压变化。 此外，还提供了用于向像素电路的复位栅极的漏极提供动态电压的这种电路的设计结构。

公开(公告)号：US07622364B2

公开(公告)日：2009-11-24

申请号：US11465622

申请日：2006-08-18

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Richard J. Rassel

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Richard J. Rassel

IPC: H01L21/00

CPC classification number: H01L24/05 ,  H01L23/3114 ,  H01L23/485 ,  H01L23/562 ,  H01L23/585 ,  H01L24/03 ,  H01L2224/05553 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An electronic packaging having at least one bond pad positioned on a chip for effectuating through-wafer connections to an integrated circuit. The electronic package is equipped with an edge seal between the bond pad region and an active circuit region, and includes a crack stop, which is adapted to protect the arrangement from the entry of deleterious moisture and combination into the active regions of the chip containing the bond pads.

Abstract translation: 一种电子封装，其具有位于芯片上的至少一个接合焊盘，用于实现与集成电路的晶圆连接。 电子封装在接合焊盘区域和有源电路区域之间配备有边缘密封，并且包括裂缝停止件，其适于保护布置免受有害水分和组合进入含有 接合垫

公开(公告)号：US20090237103A1

公开(公告)日：2009-09-24

申请号：US12051868

申请日：2008-03-20

Applicant: John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Sambasivan Narayan ,  Anthony J. Perri ,  Richard J. Rassel ,  Tian Xia

Inventor： John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Sambasivan Narayan ,  Anthony J. Perri ,  Richard J. Rassel ,  Tian Xia

IPC: G01R31/26 ,  H01L23/00 ,  G06F17/50

CPC classification number: H01L22/34 ,  G01R31/2884 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor die including a semiconductor chip and a test structure, located in a scribe area, is designed and manufactured. The test structure includes an array of complementary metal oxide semiconductor (CMOS) image sensors that are of the same type as CMOS image sensors employed in another array in the semiconductor chip and having a larger array size. Such a test structure is provided in a design phase by providing a design structure in which the orientations of the CMOS image sensors match between the two arrays. The test structure provides effective and accurate monitoring of manufacturing processes through in-line testing before a final test on the semiconductor chip.

Abstract translation: 设计并制造了包括位于划线区域中的半导体芯片和测试结构的半导体管芯。 测试结构包括互补金属氧化物半导体（CMOS）图像传感器的阵列，其与在半导体芯片中的另一阵列中使用并具有较大阵列尺寸的CMOS图像传感器具有相同的类型。 通过提供CMOS图像传感器的取向在两个阵列之间匹配的设计结构，在设计阶段提供了这种测试结构。 测试结构通过在半导体芯片上的最终测试之前的在线测试来提供对制造工艺的有效和准确的监控。

公开(公告)号：US07531392B2

公开(公告)日：2009-05-12

申请号：US11276366

申请日：2006-02-27

Applicant: John J. Ellis-Monaghan ,  Mark D. Jaffe

Inventor： John J. Ellis-Monaghan ,  Mark D. Jaffe

IPC: H01L21/84

CPC classification number: H01L21/84 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/76264 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/045

Abstract: The present invention relates to semiconductor-on-insulator (SOI) substrate structures that contain surface semiconductor regions of different crystal orientations located directly on an insulator layer. The present invention also relates to methods for fabricating such SOI substrate structures, by growing an insulator layer directly on a multi-orientation bulk semiconductor substrate that comprises surface semiconductor regions of different crystal orientations located directly on a semiconductor base layer, and removing the semiconductor base layer, thereby forming a multi-orientation SOI substrate structure that comprises surface semiconductor regions of different crystal orientations located directly on the insulator layer.

Abstract translation: 本发明涉及绝缘体上半导体（SOI）衬底结构，其包含直接位于绝缘体层上的不同晶体取向的表面半导体区域。 本发明还涉及制造这种SOI衬底结构的方法，通过直接在多取向体半导体衬底上生长绝缘体层，该绝缘体层包括直接位于半导体基底层上的不同晶体取向的表面半导体区域，以及去除半导体基底 从而形成包括直接位于绝缘体层上的不同晶体取向的表面半导体区域的多取向SOI衬底结构。